US 12,183,785 B2Granted

Monolithic semiconductor device assemblies

AssigneeSemiconductor Components Industries, LLC

InventorsPeter Moens, Gordon M. Grivna, Yusheng Lin

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Abstract

In a general aspect, a semiconductor device assembly includes a first portion of a semiconductor substrate; a second portion of the semiconductor substrate, and a semiconductor device layer disposed on the first portion of the semiconductor substrate and the second portion of the semiconductor substrate. The semiconductor device layer includes a first semiconductor device disposed on the first portion of the semiconductor substrate, and a second semiconductor device disposed on the second portion of the semiconductor substrate. The assembly also includes an isolation trench defined in the semiconductor substrate that has a dielectric material disposed therein. The isolation trench is disposed between the first portion of the semiconductor substrate and the second portion of the semiconductor substrate, and electrically isolates the first portion of the semiconductor substrate from the second portion of the semiconductor substrate. The semiconductor device layer excludes the isolation trench.

Claims20

Dependent claims

A semiconductor device assembly, comprising:

a first portion of a semiconductor substrate;
a second portion of the semiconductor substrate;
a continuous semiconductor device layer having a first surface disposed on the first portion of the semiconductor substrate and the second portion of the semiconductor substrate, the continuous semiconductor device layer having a second surface opposite the first surface, the second surface including:
a first semiconductor device disposed above the first portion of the semiconductor substrate;
and
a second semiconductor device disposed above the second portion of the semiconductor substrate;
and
an isolation trench defined in the semiconductor substrate and having a dielectric material disposed therein, the isolation trench being disposed:
between the first portion of the semiconductor substrate and the second portion of the semiconductor substrate,
the isolation trench electrically isolating the first portion of the semiconductor substrate from the second portion of the semiconductor substrate, the continuous semiconductor device layer excluding the isolation trench, and the first surface of the continuous semiconductor device layer being further disposed on the dielectric material.

7 more elements

A semiconductor device assembly comprising:

a first portion of a semiconductor substrate;
a second portion of the semiconductor substrate, the semiconductor substrate excluding a buried oxide layer;
a thermally conductive dielectric layer disposed on:
a surface of the first portion of the semiconductor substrate;
a surface of the second portion of the semiconductor substrate;
and
a surface of a dielectric material disposed in an isolation trench, the isolation trench between disposed between the first portion of the semiconductor substrate and the second portion of the semiconductor substrate;
and
a continuous semiconductor device layer having a first surface disposed on:
the first portion of the semiconductor substrate opposite the thermally conductive dielectric layer;
the second portion of the semiconductor substrate opposite the thermally conductive dielectric layer;
and
the dielectric material opposite the thermally conductive dielectric layer,
the continuous semiconductor device layer having second surface opposite the first surface, the second surface including:
a first semiconductor device disposed above the first portion of the semiconductor substrate;
and
a second semiconductor device disposed above the second portion of the semiconductor substrate,
the second semiconductor device being electrically coupled with the first semiconductor device.

15 more elements

Dependencies are inferred from the claim text.

Facts

Application: 18/340,650Filed 23 Jun 2023 · division
Priority: 14 Jul 2020
Published: US 2023/0352525 A12 Nov 2023
Granted: 31 Dec 2024
Term ends: Not estimatedThe source records don’t support an estimate.

Classification12 codes

H10D 62/115
Isolations within a component, i.e. internal isolations: dielectric isolations, e.g. air gaps
H10D 62/8503
Being Group III-V materials, e.g. GaAs: nitride Group III-V materials, e.g. AlN or GaN
H10P 54/00
Cutting or separating of wafers, substrates or parts of devices
H10W 10/014
Of isolation regions comprising dielectric materials: using trench refilling with dielectric materials, e.g. shallow trench isolations

Family

Application62/705,758Us provisional application · filed 14 Jul 2020
Application16/948,801Parent of this division · filed 1 Oct 2020
US 2023/0352525 A1Pre-grant publication · published 2 Nov 2023
US 11,742,381 B2Parent of this division
US 2022/0020848 A1Published application
US 12,183,785 B2This patent

From the US filing history. Foreign family members aren’t listed.

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