Integrated circuit with FEOL resistor

A method, comprising:

• forming a first sacrificial gate structure over an active region in a semiconductor substrate and a second sacrificial gate structure over a passive region;
• forming first source/drain regions in the active region and second source/drain regions in the passive region;
• after forming the first and second source/drain regions, replacing the first sacrificial gate structure with a metal gate structure and the second sacrificial gate structure with a metal resistor structure, the metal resistor structure corresponding to a dummy gate;
• forming a first interlayer dielectric (ILD) layer over the metal gate structure and the metal resistor structure;
• etching the first ILD layer to form contact openings in the ILD layer, wherein the contact openings expose one region of the metal gate structure and two regions of the metal resistor structure;
• and
• depositing a metal material into the contact openings to form a gate contact over the metal gate structure and two resistor contacts over the metal resistor structure.

A method, comprising:

• forming a shallow trench isolation (STI) region in a semiconductor substrate thereby defining an active region and a passive region in the semiconductor substrate and spaced apart from each other by the STI region;
• forming a first sacrificial gate structure over the active region and a second sacrificial gate structure over the passive region;
• forming first source/drain regions in the active region and second source/drain regions in the passive region;
• after forming the first and second source/drain regions, replacing the first sacrificial gate structure with a metal gate structure and the second sacrificial gate structure with a metal resistor structure, the metal resistor structure corresponding to a dummy gate;
• forming a first gate contact over the metal gate structure, and a pair of resistor contacts over the metal resistor structure;
• and
• electrically coupling a set of metal lines with the metal resistor structure by the pair of resistor contacts;
• wherein forming the first gate contact over the metal gate structure, and the pair of resistor contacts over the metal resistor structure comprises:
• forming an interlayer dielectric (ILD) layer over the metal gate structure and the metal resistor structure;
• etching the ILD layer thereby forming contact openings in the ILD layer, wherein the contact openings expose one region of the metal gate structure and two regions of the metal resistor structure;
• and
• depositing a metal material into the contact openings thereby forming the first gate contact over the metal gate structure and the pair of resistor contacts over the metal resistor structure.