Channel pattern design to improve carrier transfer efficiency

An image sensor integrated chip, comprising:

• a photodiode region disposed within a silicon substrate;
• a patterned doped silicon layer disposed on the silicon substrate, the patterned doped silicon layer having sidewalls directly overlying the photodiode region;
• a germanium region disposed onto the patterned doped silicon layer, wherein the germanium region comprises a protrusion extending outward from a lower surface of the germanium region to directly between the sidewalls of the patterned doped silicon layer;
• a first interconnect coupled to a doped region, the doped region extending from the first interconnect to the photodiode region;
• and
• a second interconnect coupled to a first doped contact region, the first doped contact region disposed within the germanium region directly over both the photodiode region and the protrusion of the germanium region.

A method of forming an image sensor integrated chip, comprising:

• forming a photodiode region within a substrate comprising a first semiconductor material region;
• forming a doped layer along an outer surface of the substrate and over the photodiode region;
• patterning the doped layer to form a patterned doped layer having one or more sidewalls that define one or more channel openings that extend through the patterned doped layer directly over the photodiode region;
• and
• forming a second semiconductor material region onto the patterned doped layer and within the one or more channel openings.