Semiconductor structure, back-side illuminated image sensor and method for manufacturing the same

A back-side illuminated (BSI) image sensor, comprising:

• a back end of line (BEOL) metallization stack;
• a semiconductor substrate arranged over the BEOL metallization stack, the semiconductor substrate including:
• a sensing region arranged at a center of the BSI image sensor and configured to sense incident radiation;
• an interconnect region surrounding the sensing region, the interconnect region including a conductive pad and an isolation region, wherein the conductive pad includes an upper conductive region above the isolation region and a lower conductive region penetrating through the isolation region, and a bottom of the lower conductive region is below a lower surface of the isolation region;
• a barrier layer surrounding the conductive pad;
• a buffer layer surrounding an upper portion of the barrier layer, and the upper portion of the barrier layer lines sidewalls of the upper conductive region of the conductive pad;
• and
• a logic region surrounding the sensing region between the sensing region and the interconnect region, the logic region including logic devices configured to support operation of the BSI image sensor.

A back-side illuminated (BSI) image sensor, comprising:

• a back end of line (BEOL) metallization stack;
• a semiconductor substrate arranged over the BEOL metallization stack, the semiconductor substrate including:
• a sensing region arranged at a center of the BSI image sensor and configured to sense incident radiation;
• and
• an interconnect region surrounding the sensing region along an edge of the BSI image sensor, the interconnect region including a conductive pad and an isolation region, wherein the isolation region neighbors to a bottom surface of the semiconductor substrate, the conductive pad includes an upper conductive region and a lower conductive region, a bottom of the upper conductive region extending substantially from an upper surface of the semiconductor substrate to above the isolation region, and the lower conductive region penetrates the isolation region;
• a barrier layer surrounding sidewalls and a bottom of conductive pad;
• a buffer layer surrounding the barrier layer;
• and
• a passivation layer arranged over the buffer layer.