Array substrate

An array substrate, comprising:

• a substrate;
• a light shielding layer disposed on the substrate in a vertical direction perpendicular to an upper surface of the substrate and including a first light shielding layer and a second light shielding layer disposed at an interval in a horizontal direction perpendicular to the vertical direction;
• a buffer layer disposed above the substrate in the vertical direction and covering the light shielding layer;
• a semiconductor layer disposed on the buffer layer in the vertical direction and defining an active area and a photosensitive area in direct contact with each other, wherein the active area includes a channel area, the photosensitive area includes a P-type semiconductor area, a N-type semiconductor area, and an I-type semiconductor area defined between the P-type semiconductor area and the N-type semiconductor area in the horizontal direction, the channel area overlaps the first light shielding layer in the vertical direction, and the I-type semiconductor area overlaps the second light shielding layer in the vertical direction;
• a gate insulating layer disposed on the buffer layer and covering the semiconductor layer;
• a gate layer disposed on the gate insulating layer and located corresponding to the channel area;
• a layer insulating layer disposed on the gate insulating layer and covering the gate layer;
• a first conductive layer disposed on the semiconductor layer in the vertical direction, wherein the first conductive layer includes a source and a drain penetrating the layer insulating layer in the vertical direction, extending through the gate insulating layer in the vertical direction and respectively connected to the active area and the P-type semiconductor area in the semiconductor layer;
• a passivation layer disposed above the first conductive layer in the vertical direction;
• and
• an auxiliary adjusting electrode adjacent to and spaced apart from the first conductive layer in the horizontal direction,
• wherein the auxiliary adjusting electrode penetrates the passivation layer and extends in the vertical direction downwardly to be connected to the second light shielding layer and serve as the gate of a PIN photoelectric diode formed of the P-type semiconductor area, the N-type semiconductor area, and the I-type semiconductor area in the photosensitive area, to introduce a gate electric current at a location of the light shielding layer directly below the I-type semiconductor area, thereby adjusting a Fermi energy level of the I-type semiconductor area.

An array substrate, comprising:

• a substrate;
• a light shielding layer disposed on the substrate in a vertical direction perpendicular to an upper surface of the substrate and including a first light shielding layer and a second light shielding layer disposed at an interval in a horizontal direction perpendicular to the vertical direction;
• a buffer layer disposed above the substrate in the vertical direction and covering the light shielding layer;
• a semiconductor layer disposed on the buffer layer in the vertical direction and defining an active area and a photosensitive area in direct contact with each other, wherein the active area includes the channel area, the photosensitive area includes a P-type semiconductor area, a N-type semiconductor area, and the I-type semiconductor area defined between the P-type semiconductor area and the N-type semiconductor area in the horizontal direction, the channel area overlaps the first light shielding layer in the vertical direction, and the I-type semiconductor area overlaps the second light shielding layer in the vertical direction;
• a gate insulating layer disposed on the buffer layer and covering the semiconductor layer;
• a gate layer disposed on the gate insulating layer and located corresponding to the channel area;
• a layer insulating layer disposed on the gate insulating layer and covering the gate layer;
• a first conductive layer disposed above the semiconductor layer in the vertical direction, wherein the first conductive layer includes a source and a drain penetrating the layer insulating layer in the vertical direction, extending through the gate insulating layer in the vertical direction and respectively connected to the active area and the P-type semiconductor area in the semiconductor layer;
• a passivation layer disposed above the first conductive layer in the vertical direction;
• and
• an adjusting electrode adjacent to and spaced apart from the first conductive layer in the horizontal direction, wherein the adjusting electrode penetrates the passivation layer and extends in the vertical direction downwardly to be connected to the second light shielding layer and serve as the gate of a PIN photoelectric diode formed of the P-type semiconductor area, the N-type semiconductor area, and the I-type semiconductor area in the photosensitive area, to introduce a gate electric current at a location of the second light shielding layer directly below the I-type semiconductor area, thereby adjusting a Fermi energy level of the I-type semiconductor area.