Stacked field-effect transistors

A method of fabricating a stacked FET, the method comprising:

• forming a nanosheet stack on top of a substrate, wherein the nanosheet stack comprises a plurality of semiconductor layers separated by sacrificial layers, wherein the nanosheet stack comprises a top region, a middle region, and a bottom region, the semiconductor layers in the top region having a first thickness, the semiconductor layers in the middle region having a second thickness, and the semiconductor layers in the bottom region having a third thickness, wherein the second thickness is smaller than both the first and third thicknesses;
• patterning the nanosheet stack to form a plurality of nanosheet fins;
• indenting the sacrificial layers in between the nanosheet fins;
• forming inner spacers in the indents in the sacrificial layers;
• forming one or more bottom source/drain epitaxies between the nanosheet fins in the bottom region;
• indenting the semiconductor layers in the middle region;
• forming a bottom inter-layer dielectric (ILD) on the one or more bottom source/drain epitaxies, wherein the bottom ILD fills in the indents in the semiconductor layers;
• forming one or more top source/drain epitaxies on top of the bottom ILD;
• forming a top ILD on the one or more top source/drain epitaxies;
• removing the sacrificial layers;
• trimming the semiconductor layers such that the semiconductor layers in the middle region are removed and the semiconductor layers in the top and bottom regions are thinned;
• and
• forming a metal gate around the semiconductor layers.

A method comprising:

• forming a top device comprising a first plurality of channel sheets separated by inner spacers and a metal gate;
• forming a transition region comprising a plurality of inner spacers separated by a first distance and a first inter-layer dielectric (ILD) formed between each of the plurality of inner spacers;
• and
• forming a bottom device comprising a second plurality of channel sheet separated by inner spacers and the metal gate,
• wherein the top and bottom devices have a first channel sheet thickness in a gate region and a second channel sheet thickness between the inner spacers, the second channel sheet thickness being larger than both the first channel sheet thickness and the first distance.