Semiconductor package

A method of manufacturing a semiconductor package, the method comprising:

• forming a redistribution structure on a carrier substrate, the redistribution structure comprising a lower bump pad including a first surface and a second surface opposite each other, a redistribution pattern in contact with the second surface of the lower bump pad, a first conductive barrier layer in contact with a side surface of the lower bump pad, a second conductive barrier layer in contact with the first surface of the lower bump pad, and a first redistribution insulating layer extending between the lower bump pad and the redistribution pattern, wherein the first redistribution insulating layer directly contacts the first conductive barrier layer,
• disposing a semiconductor chip on the redistribution structure;
• forming a molding layer on the redistribution structure, the molding layer surrounding the side surface of the semiconductor chip;
• separating the carrier substrate from the redistribution structure;
• forming a first opening in a second redistribution insulating layer, the first opening exposing a central portion of the first surface of the lower bump pad;
• and
• forming an external connection bump filling the first opening of the second redistribution insulating layer and in direct contact with the central portion of the first surface of the lower bump pad,
• wherein the first conductive barrier layer does not extend between the lower bump pad and the external connection bump.

A method of manufacturing a semiconductor package, the method comprising:

• forming a first redistribution insulating layer on a carrier substrate;
• forming a mask pattern on the first redistribution insulating layer, the mask pattern including a mask opening;
• forming a lower bump pad in the mask opening of the mask pattern, the lower bump pad including a first surface facing the first redistribution insulating layer and a second surface opposite the first surface;
• removing the mask pattern;
• forming a first conductive barrier layer extending along the side surface of the lower bump pad and in contact with the side surface of the lower bump pad;
• forming a second redistribution insulating layer on the first redistribution insulating layer and the lower bump pad, the second redistribution insulating layer including a via opening that exposes a part of the second surface of the lower bump pad;
• forming a redistribution pattern that comprises a conductive via pattern and a conductive line pattern, the conductive via pattern extending in a vertical direction in the via opening of the second redistribution insulating layer, and the conductive line pattern extending along a surface of the second redistribution insulating layer and being connected to the conductive via pattern;
• disposing a semiconductor chip on the second redistribution insulating layer;
• forming a molding layer on the second redistribution insulating layer, the molding layer surrounding a side surface of the semiconductor chip;
• removing the carrier substrate;
• forming a first opening in the first redistribution insulating layer;
• and
• forming an external connection bump filling the first opening of the first redistribution insulating layer and in contact with the first surface of the lower bump pad.