Semiconductor package and manufacturing method thereof

A semiconductor package, comprising:

• semiconductor dies, laterally spaced apart from one another, and comprising die inputs/outputs (I/Os) at active sides of the semiconductor dies;
• and
• a redistribution structure, disposed at the active sides of the semiconductor dies and connected to the die I/Os, wherein the redistribution structure comprises a first routing layer and a second routing layer sequentially arranged along a direction away from the die I/Os,
• wherein the first routing layer comprises a ground plane and first signal lines, the first signal lines are laterally surrounded by and isolated from the first ground plane, a first terminal of each first signal line is positioned in correspondence with one of the die I/Os and located within a central region of the redistribution structure, and the first signal lines extending from the first terminals are bounded at second terminals arranged along a same lateral side of the redistribution structure, and
• wherein the second routing layer comprises second signal lines and ground lines each having two terminals arranged along the lateral side of the redistribution structure, the second signal lines each extend from the second terminal of one of the first signal lines to the second terminal of another one of the first signal lines through the central region of the redistribution structure, and the ground lines each extend between adjacent ones of the second signal lines.

A semiconductor package, comprising:

• a first semiconductor die and a second semiconductor die, laterally spaced apart from each other and encapsulated by an encapsulant, wherein first die I/Os of the first semiconductor dies and second die I/Os of the second semiconductor die extend to a front side of the encapsulant;
• a first routing layer, disposed at the front side of the encapsulant, and comprising a first ground plane and first signal lines extending in openings defined in the first ground plane, wherein the first signal lines extend from first terminals respectively positioned in correspondence with one of the first and second die I/Os and located within a central region of the first routing layer, and are bounded at second terminals arranged along a same lateral side of the first routing layer;
• and
• a second routing layer, disposed at a side of the first routing layer facing away from the encapsulant, and comprising second signal lines and first ground lines extending along and in parallel with the second signal lines, wherein the second signal lines respectively connect the second terminal of one of the first signal lines routed from one of the first die I/Os to the second terminal of another one of the first signal lines routed from one of the second die I/Os, and are each bounded at two terminals arranged along a same lateral side of the second routing layer while passing through a central region of the second routing layer.