Backside power rail structure and methods of forming same

A semiconductor device comprising:

• a power rail;
• an isolation layer over the power rail;
• a first channel region over the isolation layer;
• a second channel region over the first channel region;
• a gate stack disposed between the first channel region and the second channel region, and over the second channel region;
• and
• a first source/drain region adjacent the first channel region and the second channel region, the first source/drain region extending between a first portion of the isolation layer and a second portion of the isolation layer, wherein the first portion of the isolation layer has a trapezoid shape.

A semiconductor device comprising:

• a first channel region over a first dielectric layer;
• a second channel region over the first channel region;
• a gate stack disposed between the first channel region and the second channel region, and over the second channel region;
• a first source/drain region and a second source/drain region on opposite sides of the first dielectric layer, the first channel region, the second channel region, and the gate stack;
• and
• a backside power rail on an opposite side of the first dielectric layer as the first channel region, wherein the backside power rail is electrically coupled to the first source/drain region, wherein a thickness of the first dielectric layer is greater than a thickness of the first channel region.