Fan-out packages with warpage resistance
AssigneeAdvanced Micro Devices, Inc.
InventorsRahul Agarwal, Chia-Hao Cheng, Milind S. Bhagavat
Life of this patent
Estimating the term…
Abstract
Various molded fan-out semiconductor chip devices are disclosed. In one aspect, a semiconductor chip device is provided that includes a first molding layer that has internal conductor structures, a redistribution layer (RDL) structure positioned on the first molding layer and electrically connected to the internal conductor structures, a semiconductor chip positioned on and electrically connected to the RDL structure, and a second molding layer positioned on the RDL structure and at least partially encapsulating the semiconductor chip.
Claims18
A semiconductor chip device, comprising:
- a single semiconductor chip;
- a first molding layer having internal conductor structures;
- a first redistribution layer (RDL) structure positioned on the first molding layer and including fan-out connections to the internal conductor structures;
- a second RDL structure positioned on the first RDL structure and including fan-out connections to the first RDL structure, the single semiconductor chip positioned on and electrically connected to the second RDL structure, wherein the first RDL structure is connected to the internal conductor structures of the first molding layer and to the second RDL structure;
- and
- a second molding layer positioned on the second RDL structure and at least partially encapsulating the semiconductor chip.
A method of manufacturing a semiconductor chip device, comprising:
- forming a first molding layer having internal conductor structures;
- forming a first redistribution layer (RDL) structure on the first molding layer and including fan-out connections to the internal conductor structures;
- forming, after forming the first RDL structure on the first molding layer, a second RDL structure on the first RDL structure and including fan-out connections to the first RDL structure, wherein the first RDL structure is connected to the internal conductor structures of the first molding layer and to the second RDL structure;
- mounting a semiconductor chip on and in electrical connection with the second RDL structure;
- and
- forming a second molding layer on the second RDL structure and at least partially encapsulating the semiconductor chip.
A computer system, comprising:
- a system board;
- wherein the system board comprises one or more chip packages, wherein at least one of the one or more chip packages comprises:
- a single semiconductor chip;
- a first molding layer having internal conductor structures;
- a first redistribution layer (RDL) structure positioned on the first molding layer and including fan-out connections to the internal conductor structures;
- a second RDL structure positioned on the first RDL structure and including fan-out connections to the first RDL structure, the single semiconductor chip positioned on and electrically connected to the second RDL structure, wherein the first RDL structure is connected to the internal conductor structures of the first molding layer and to the second RDL structure;
- and
- a second molding layer positioned on the second RDL structure and at least partially encapsulating the semiconductor chip.
Dependencies are inferred from the claim text.