Hybrid metal line structure

An integrated chip comprising:

• a substrate;
• a first metal line over the substrate, the first metal line comprising a first metal;
• a first dielectric layer over the substrate and beside the first metal line;
• and
• a hybrid metal line over the substrate and laterally spaced from the first metal line by the first dielectric layer, the hybrid metal line comprising:
• a first metal segment comprising a second metal, different from the first metal;
• a second metal segment on a first side of the first metal segment, the second metal segment comprising the first metal, wherein a top surface of the second metal segment has a first width and a bottom surface of the second metal segment has a second width;
• and
• a third metal segment on a second side of the first metal segment, opposite the first side, the third metal segment comprising the first metal, wherein a top surface of the third metal segment has a third width, greater than the first width, and a bottom surface of the third metal segment has a fourth width, greater than the second width.

An integrated chip comprising:

• a substrate;
• a first dielectric layer over the substrate;
• a first metal line over the substrate, the first metal line comprising a first metal;
• and
• a hybrid metal line over the substrate, the first dielectric layer between the hybrid metal line and the first metal line, the hybrid metal line comprising:
• a second metal line comprising a second metal, different than the first metal;
• and
• a third metal line and a fourth metal line on opposite sides of the second metal line and coupled to the second metal line, the third metal line and the fourth metal line comprising the first metal,
• wherein a width of the hybrid metal line along a bottom of the hybrid metal line is greater than a width of the hybrid metal line along a top of the hybrid metal line.