Semiconductor package
AssigneeSamsung Electronics Co., Ltd.
InventorsMyungsam Kang, Youngchan Ko, Jeongseok Kim, Kyung Don Mun
Life of this patent
Estimating the term…
Loading patent…
AssigneeSamsung Electronics Co., Ltd.
InventorsMyungsam Kang, Youngchan Ko, Jeongseok Kim, Kyung Don Mun
Estimating the term…
Disclosed is a semiconductor package comprising a package substrate, an interposer substrate on the package substrate and including a first redistribution substrate, a second redistribution substrate on a bottom surface of the first redistribution substrate, and an interposer molding layer between the first redistribution substrate and the second redistribution substrate, a connection substrate on the interposer substrate and having a connection hole that penetrates the connection substrate, a first semiconductor chip on the interposer substrate and in the connection hole, a second semiconductor chip on the interposer substrate, in the connection hole and horizontally spaced apart from the first semiconductor chip, and a connection semiconductor chip in the interposer molding layer and on the bottom surface of the first redistribution substrate.
A method of manufacturing a semiconductor package, comprising:
A method of manufacturing a semiconductor package, comprising:
Dependencies are inferred from the claim text.