Semiconductor package

A semiconductor package, comprising:

• a redistribution substrate;
• a semiconductor chip mounted on a top surface of the redistribution substrate;
• and
• a conductive terminal provided on a bottom surface of the redistribution substrate,
• wherein the redistribution substrate comprises:
• an under-bump pattern including a first via portion in contact with the conductive terminal and a wire portion on the first via portion;
• an insulating layer contacting a side surface of the under-bump pattern;
• and
• redistribution patterns provided on the under-bump pattern,
• wherein the uppermost redistribution patterns of the redistribution patterns are connected to the semiconductor chip,
• wherein at least one of the uppermost redistribution patterns comprises a second via portion and a pad portion on the second via portion,
• wherein the wire portion comprises a seed pattern and a conductive pattern on the seed pattern,
• wherein side surfaces of the seed pattern and the conductive pattern of the wire portion are aligned in a vertical direction,
• wherein the bottom surface of the first via portion is curvedly recessed in a direction toward the wire portion,
• wherein the conductive terminal contacts the seed pattern and the conductive pattern of the first via portion of the under-bump pattern,
• wherein an uppermost surface of the conductive terminal is at a higher level than a lowermost surface of the insulating layer, and
• wherein only a top surface of the conductive pattern of the pad portion of the at least one of the uppermost redistribution patterns includes a recessed portion.

A semiconductor package, comprising:

• a redistribution substrate;
• a semiconductor chip mounted on a top surface of the redistribution substrate;
• a chip connection terminal provided between the redistribution substrate and the semiconductor chip;
• an under-fill layer surrounding the chip connection terminal;
• a mold layer covering side and top surfaces of the semiconductor chip and side surfaces of the under-fill layer;
• and
• a conductive terminal provided on a bottom surface of the redistribution substrate,
• wherein the redistribution substrate comprises:
• an under-bump pattern including a via portion in contact with the conductive terminal and a wire portion on the via portion;
• redistribution patterns provided on the under-bump pattern;
• and
• an insulating layer covering the under-bump pattern and the redistribution patterns,
• wherein each of the redistribution patterns comprises a via portion, which is in contact with another one of the redistribution patterns adjacent thereto or the under-bump pattern, and a wire portion, which is provided on the via portion,
• wherein a central portion of a bottom surface of the via portion of the under-bump pattern is provided at a level higher than an edge portion of the bottom surface of the via portion of the under-bump pattern,
• wherein the bottom surface of the via portion is curvedly recessed in a direction toward the wire portion,
• wherein the via portion comprises a seed pattern and a conductive pattern on the seed pattern, and
• wherein the conductive terminal contacts the seed pattern and the conductive pattern of the via portion.