Selective hybrid capping layer for metal gates of transistors

A method comprising:

• forming a gate dielectric over a semiconductor region;
• forming a gate electrode comprising:
• forming a first portion comprising a work-function layer therein;
• and
• forming a second portion overlying and contacting top surfaces of the first portion, wherein the second portion comprises fluorine and chlorine, and wherein the forming the second portion comprises:
• depositing a bottom sub layer;
• and
• depositing a top sub layer over and contacting the bottom sub layer, wherein the top sub layer comprises an element different from elements in the bottom sub layer;
• and
• forming a gate contact plug over and contacting the top sub layer.

A method comprising:

• forming isolation regions extending into a semiconductor substrate;
• recessing the isolation regions to form a semiconductor fin on opposing sides of the semiconductor fin, wherein the semiconductor fin protrudes higher than remaining portions of the isolation regions;
• and
• forming a gate stack comprising:
• a high-k gate dielectric on the semiconductor fin;
• and
• a work function layer on the high-k gate dielectric;
• depositing a first tungsten layer over and contacting the gate stack;
• and
• depositing a second tungsten layer over and contacting the first tungsten layer, wherein the first tungsten layer and the second tungsten layer are distinguishable from each other.