Shared decoder circuit and method

A circuit comprising:

• a series configuration of a first latch circuit, a selection circuit, a second latch circuit, and a pre-decoder;
• and
• a control circuit configured to, based on a clock signal having a clock period:
• output a select signal to the selection circuit and first and second clock pulse signals to the respective first and second latch circuits, and
• output, to the pre-decoder, a third clock pulse signal comprising:
• a first pulse during a first portion of the clock period in response to a read enable signal having a first logical state;
• and
• a second pulse during a second portion of the clock period in response to a write enable signal having the first logical state,
• wherein
• the selection circuit and first and second latch circuits are configured to, based on the select and first and second clock pulse signals, output read and write addresses to the pre-decoder during the respective first and second clock period portions, and
• the pre-decoder is configured to output a partially decoded address in response to each of
• the read address and the first pulse, and
• the write address and the second pulse.

A method of operating a memory circuit, the method comprising:

• receiving a clock signal and read and write enable signals at a control circuit of the memory circuit;
• outputting control signals from the control circuit to a selection circuit and first and second latch circuits of the memory circuit;
• outputting, from the control circuit to a pre-decoder of the memory circuit, a first clock pulse signal comprising:
• a first pulse during a first portion of a clock period of the clock signal in response to the read enable signal having a low logical state, and
• a second pulse during a second portion of the clock period in response to the write enable signal having the low logical state,
• in response to the control signals, outputting read and write addresses from the selection circuit and first and second latch circuits to the pre-decoder during the respective first and second clock period portions;
• and
• outputting a partially decoded address from the pre-decoder in response to each of
• the read address and the first pulse, and
• the write address and the second pulse.