Memory circuit and method of operating the same

A memory circuit, comprising:

• a NAND logic gate configured to receive a first bit line signal and a second bit line signal, and to generate a first signal responsive to the first bit line signal and the second bit line signal;
• a first P-type transistor coupled to the NAND logic gate, and configured to receive a first clock signal;
• a first N-type transistor having a first drain coupled to a first voltage supply node of the NAND logic gate, a first gate configured to receive a first input signal, and a first source coupled to a first node;
• a second N-type transistor having a second drain coupled to the first source and the first node, a second gate configured to receive a second clock signal inverted from the first clock signal, and a second source coupled to a reference voltage supply;
• and
• a first latch coupled to the NAND logic gate by a second node, and configured to latch the first signal in response to at least the first input signal.

A method of operating a memory circuit, the method comprising:

• receiving, by a NAND logic gate circuit, a first bit line signal and a second bit line signal;
• generating, by the NAND logic gate circuit, a first signal in response to the first bit line signal and the second bit line signal, wherein generating the first signal comprises:
• enabling the NAND logic gate circuit in response to a first clock signal and at least a first pre-charge signal or a second pre-charge signal different from the first pre-charge signal;
• and
• latching, by a latch, a state of the first signal in response to the first clock signal or at least the first pre-charge signal or the second pre-charge signal, the latch including a first inverter and a second inverter.