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US 12,183,427 B1Granted
System and method for write clock double data rate duty cycle correction
AssigneeCadence Design Systems, Inc.
InventorsSachin Ramesh Gugwad, Hari Anand Ravi
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Abstract
The present disclosure relates to a system and method for duty cycle correction is provided. The method may include receiving a signal at a duty cycle adjuster and performing serializer clock duty cycle correction at the duty cycle adjuster. The method may further include performing true clock duty cycle correction at a transmitter duty cycle adjuster and performing complementary duty cycle distortion correction at the transmitter duty cycle adjuster.
Claims18
A duty cycle correction method, comprising:
- receiving a signal at a duty cycle adjuster;
- performing serializer clock duty cycle correction at the duty cycle adjuster;
- performing true clock duty cycle correction at a transmitter duty cycle adjuster, wherein the transmitter duty cycle adjuster is included within a write clock (WCK) transmit path;
- and
- performing complementary duty cycle distortion correction at the transmitter duty cycle adjuster.
2 more elements
A duty cycle correction system, comprising:
- a duty cycle adjuster configured to receive a signal and to perform serializer clock duty cycle correction;
- and
- a transmitter duty cycle adjuster configured to perform true clock duty cycle correction, wherein the transmitter duty cycle adjuster is further configured to perform complementary duty cycle distortion correction, wherein the transmitter duty cycle adjuster is included within a write clock (WCK) transmit path.
Dependencies are inferred from the claim text.