Data reading/writing method, memory, storage apparatus, and terminal

A storage apparatus, comprising:

• a memory;
• a storage controller coupled to the memory;
• the memory comprises:
• S storage blocks,
• N global bitlines, and
• a signal amplification circuit,
• each of the S storage blocks is connected to the N global bitlines,
• the N global bitlines are connected to the signal amplification circuit,
• the signal amplification circuit is configured to amplify electrical signals on the N global bitlines,
• S and N are positive integers, and S≥2,
• each storage block comprises N columns of storage units,
• N local bitlines,
• N bitline switches coupled to the N local bitlines and N global bitlines;
• and
• in each storage block,
• storage units in an ith column in the N columns of storage units are connected to an ith local bitline in the N local bitlines, the ith local bitline is connected to an ith global bitline in the N global bitlines via an ith bitline switch in the N bitline switches, N is a positive integer, and i is a positive integer not greater than N;
• and
• wherein:
• each storage block is divided into T storage sub-blocks, the storage sub-blocks in the memory are arranged in S rows×T columns, each column of storage sub-blocks forms one storage domain, the memory comprises T storage domains, the memory further comprises W global wordlines, T and W are positive integers, T≥2, and each of the T storage domains comprises W rows of storage units, W local wordlines, and W wordline switches;
• and
• in each storage domain, storage units in a vth row in the W rows of storage units are connected to a vth local wordline in the W local wordlines, the vth local wordline is connected to a vth global wordline in the W global wordlines by using a vth wordline switch in the W wordline switches, W is a positive integer, and v is a positive integer not greater than W.

A terminal, comprising a processor, a storage controller and a memory, wherein the memory is coupled to the processor, wherein the memory comprises S storage blocks, N global bitlines, and a signal amplification circuit, wherein each of the S storage blocks is connected to the N global bitlines, the N global bitlines are connected to the signal amplification circuit, the signal amplification circuit is configured to amplify electrical signals on the N global bitlines, S and N are positive integers, S≥2, and each storage block comprises N columns of storage units, N local bitlines, and N bitline switches;

• and
• in each storage block, storage units in an ith column in the N columns of storage units are connected to an ith local bitline in the N local bitlines, the ith local bitline is connected to an ith global bitline in the N global bitlines by using an ith bitline switch in the N bitline switches, N is a positive integer, and i is a positive integer not greater than N;
• and
• wherein:
• each storage block is divided into T storage sub-blocks, the storage sub-blocks in the memory are arranged in S rows×T columns, each column of storage sub-blocks forms one storage domain, the memory comprises T storage domains, the memory further comprises W global wordlines, T and W are positive integers, T≥2, and each of the T storage domains comprises W rows of storage units, W local wordlines, and W wordline switches;
• and
• in each storage domain, storage units in a vth row in the W rows of storage units are connected to a vth local wordline in the W local wordlines, the vth local wordline is connected to a vth global wordline in the W global wordlines by using a vth wordline switch in the W wordline switches, W is a positive integer, and v is a positive integer not greater than W.