Bit-cell architecture based in-memory compute

A memory array, comprising:

• a plurality of bit-cells of the memory array arranged as a set of rows of bit-cells of the memory array intersecting a plurality of columns of the memory array;
• and
• a plurality of in-memory-compute (IMC) cells of the memory array arranged as a set of rows of IMC cells of the memory array intersecting the plurality of columns of the memory array, wherein each of the IMC cells of the memory array includes:
• a first bit-cell having a latch, a write-bit line and a complementary write-bit line;
• and
• a second bit-cell having a latch, a write-bit line and a complementary write-bit line, wherein the write-bit line of the first bit-cell is coupled to the complementary write-bit line of the second bit-cell and the complementary write-bit line of the first bit-cell is coupled to the write-bit line of the second bit-cell, wherein, the first bit-cells of the IMC cells comprise a read-word line, and the second bit-cells of the IMC cells comprise a read-word line, and, in an in-memory-compute mode of operation of the array, the IMC cells selectively XOR data stored in the latches with data provided on the read-word lines.

A system, comprising:

• a plurality of in-memory-compute (IMC) memory arrays, each IMC memory array including:
• a plurality of bit-cells arranged as a set of rows of bit-cells intersecting a plurality of columns of the IMC memory array;
• and
• a plurality of in-memory-compute (IMC) cells of the IMC memory array arranged as a set of rows of IMC cells intersecting the plurality of columns of the IMC memory array, each of the IMC cells of the IMC memory array having:
• a first bit-cell having a latch, a write-bit line and a complementary write-bit line;
• and
• a second bit-cell having a latch, a write-bit line and a complementary write-bit line, wherein the write-bit line of the first bit-cell is coupled to the complementary write-bit line of the second bit-cell and the complementary write-bit line of the first bit-cell is coupled to the write-bit line of the second bit-cell;
• and
• accumulation circuitry coupled to the columns of the plurality of IMC memory arrays, wherein the first bit-cells of the IMC cells comprise a read-word line, and the second bit-cells of the IMC cells comprise a read-word line, and, in an in-memory-compute mode of operation of the system, the IMC cells selectively XOR data stored in the latches with data provided on the read-word lines.

A system, comprising:

• a plurality of in-memory-compute (IMC) memory arrays, each IMC memory array including:
• a plurality of bit-cells arranged as a set of rows of bit-cells intersecting a plurality of columns of the IMC memory array;
• and
• a plurality of in-memory-compute (IMC) cells of the IMC memory array arranged as a set of rows of IMC cells intersecting the plurality of columns of the IMC memory array, each of the IMC cells of the IMC memory array having:
• a first bit-cell having a latch, a write-bit line and a complementary write-bit line;
• and
• a second bit-cell having a latch, a write-bit line and a complementary write-bit line, wherein the write-bit line of the first bit-cell is coupled to the complementary write-bit line of the second bit-cell and the complementary write-bit line of the first bit-cell is coupled to the write-bit line of the second bit-cell;
• and
• accumulation circuitry coupled to the columns of the plurality of IMC memory arrays, wherein the plurality of IMC memory arrays comprise pre-charging circuitry coupled to the plurality of IMC cells.

A method, comprising:

• storing weight data in a plurality of rows of an in-memory-compute (IMC) memory array arranged as a plurality of rows of cells intersecting a plurality of columns of cells, the IMC memory array include a set of rows of bit-cells and a set of rows of IMC cells, wherein each of the IMC cells of the IMC memory array includes:
• a first bit-cell having a latch, a write-bit line and a complementary write-bit line;
• and
• a second bit-cell having a latch, a write-bit line and a complementary write-bit line, wherein the write-bit line of the first bit-cell is coupled to the complementary write-bit line of the second bit-cell and the complementary write-bit line of the first bit-cell is coupled to the write-bit line of the second bit-cell;
• storing feature data in one or more rows of the set of rows of IMC cells;
• and
• multiplying, using an IMC cell of a column of the IMC memory array, feature data stored in the IMC cell and weight data stored in the column of the IMC cell, wherein the first bit-cell of the IMC cell comprises a read-word line, and the second bit-cell of the IMC cell comprises a read-word line, and, the multiplying includes XORing data stored in the latches of the IMC cell with data provided on the read-word lines of the IMC cell.

A non-transitory computer-readable medium having contents, which, in operation, configure a computing system to perform a method, the method comprising:

• storing weight data in a plurality of rows of an in-memory-compute (IMC) memory array arranged as a plurality of rows of cells intersecting a plurality of columns of cells, the IMC memory array include a set of rows of bit-cells and a set of rows of IMC cells, wherein each of the IMC cells of the IMC memory array includes:
• a first bit-cell having a latch, a write-bit line and a complementary write-bit line;
• and
• a second bit-cell having a latch, a write-bit line and a complementary write-bit line, wherein the write-bit line of the first bit-cell is coupled to the complementary write-bit line of the second bit-cell and the complementary write-bit line of the first bit-cell is coupled to the write-bit line of the second bit-cell;
• storing feature data in one or more rows of the set of rows of IMC cells;
• and
• multiplying, using an IMC cell of a column of the IMC memory array, feature data stored in the IMC cell and weight data stored in the column of the IMC cell, wherein the first bit-cell of the IMC cell comprises a read-word line, and the second bit-cell of the IMC cell comprises a read-word line, and, the multiplying includes XORing data stored in the latches of the IMC cell with data provided on the read-word lines of the IMC cell.