Memory array with compensated word line access delay

A method comprising:

• receiving, by a controller of a memory device, an indication to read a stored value of a first memory cell of a plurality of memory cells of a memory array;
• providing, by the controller, one or more address signals indicative of a word line and a digit line of the first memory cell to a row decoder and column decoder circuitry of the memory array to access the first memory cell;
• determining, by the controller, that the first memory cell is coupled to a first sense component associated with the column decoder circuitry;
• selecting, by the controller, a delayed latching signal to latch the stored value of the first memory cell by the first sense component based on a delayed latching time in response to determining that the first memory cell is coupled to the first sense component;
• and
• receiving, by the controller, the stored value on the first memory cell.

A memory device, comprising:

• a first word line;
• a first digit line;
• a plurality of memory cells, wherein a first memory cell of the plurality of memory cells is coupled to the first word line and the first digit line;
• a first word line driver coupled to the first word line, wherein the first word line driver is configured to apply a voltage to the first memory cell via the first word line, and wherein the first memory cell is configured to provide a first digit line voltage indicative of a first stored value to the first digit line based on receiving the applied voltage;
• and
• a first sense component coupled to the first digit line, the first sense component comprising first latching circuitry configured to latch the first digit line voltage based on a latching time or a delayed latching time based on a first selection signal.