Programmable column access

A memory device, comprising:

• a memory array comprising a row of memory cells coupled with respective digit lines;
• a controller coupled with the memory array and configured to concurrently communicate each respective control signal of a set of respective control signals to each respective multiplexer via a single selection line associated with the respective multiplexer of a set of multiplexers coupled with the digit lines, wherein each respective control signal is received at the respective multiplexer via the respective single selection line and comprises a numerical bit sequence indicating a single digit line of a subset of the digit lines coupled with the respective multiplexer based on each digit line of the subset of the digit lines being associated with a respective numerical bit sequence;
• a first multiplexer of the set of multiplexers, that is coupled with the controller and a first subset of the digit lines, the first multiplexer configured to couple a first digit line of the first subset of the digit lines with a first sense component based on the numerical bit sequence of a first control signal of the set of respective control signals, wherein the first multiplexer couples the first digit line concurrently with a second multiplexer of the set of multiplexers;
• and
• the second multiplexer of the set of multiplexers, coupled with the controller and a second subset of the digit lines, the second multiplexer configured to couple a second digit line of the second subset of the digit lines with a second sense component based on the numerical bit sequence of a second control signal of the set of respective control signals, wherein the second multiplexer couples the second digit line concurrently with the first multiplexer.

A memory device, comprising:

• a memory array comprising a row of memory cells coupled with a set of multiplexers;
• and
• one or more controllers coupled with the memory array and the set of multiplexers, the one or more controllers operable to cause the memory device to:
• transfer voltages from memory cells of a row in the memory array to respective digit lines for the memory cells, the voltages indicative of logic values stored at the memory cells;
• communicate respective control signals concurrently to each respective multiplexer via a single selection line associated with the respective multiplexer of the set of multiplexers, wherein each multiplexer is coupled with a respective subset of the digit lines and wherein each respective control signal is received at the respective multiplexer via the respective single selection line and comprises a numerical bit sequence indicating a single digit line of the respective subset of the digit lines based on each digit line of the respective subset of the digit lines being associated with a respective numerical bit sequence;
• and
• couple, concurrently by each multiplexer and based on the numerical bit sequence of the control signal for that multiplexer, a digit line of the respective subset of digit lines with a sense component for that multiplexer.