US 12,183,417 B2 · Memory device and manufacturing method of the same

Abstract

A memory device in an integrated circuit is provided, including an input/output (I/O) circuit, a first memory segment and a second memory segment that separated from the first memory segment in a first direction, a first pair of data lines on a first side of the integrated circuit, extending in the first direction and configured to couple the first memory segment to the I/O circuit, and a second pair of data lines separated from the first pair of data lines in a second direction, different from the first direction, on a second side, opposite to the first side, of the integrated circuit, and configured to couple the second memory segment to the I/O circuit. A first width of the first pair of data lines is different from a second width of the second pair of data lines.

Claims20

Dependent claims

A memory device in an integrated circuit, comprising:

an input/output (I/O) circuit;
a first memory segment and a second memory segment that is separated from the first memory segment in a first direction;
a first pair of data lines on a first side of the integrated circuit, extending in the first direction and configured to couple the first memory segment to the I/O circuit;
and
a second pair of data lines separated from the first pair of data lines in a second direction, different from the first direction, on a second side, opposite to the first side, of the integrated circuit, and configured to couple the second memory segment to the I/O circuit,
wherein a first width of the first pair of data lines is different from a second width of the second pair of data lines.

3 more elements

A memory device in an integrated circuit, comprising:

a first pair of complementary data lines that are arranged in a first layer on a first side of the integrated circuit and coupled to a plurality of first memory cells in a first column;
and
a second pair of complementary data lines that are arranged in a first layer on a second side, opposite to the first side, of the integrated circuit and coupled to a plurality of second memory cells in the first column,
wherein lengths of the first and second pairs of complementary data lines are different from each other, and widths of the first and second pairs of complementary data lines are different from each other.

1 more element

Dependencies are inferred from the claim text.

Facts

Application

17/882,156Filed 5 Aug 2022

Published

US 2024/0046969 A18 Feb 2024

Granted

31 Dec 2024

Term ends

Not estimatedThe source records don’t support an estimate.

Classification12 codes

G11C 5/063
Arrangements for interconnecting storage elements electrically, e.g. by wiring: voltage and signal distribution in integrated semi-conductor…
G11C 7/10
Arrangements for writing information into, or reading information out from, a digital store: input/output [I/O] data interface arrangements, e.g.…
G11C 5/025
Disposition of storage elements, e.g. in the form of a matrix array: geometric lay-out considerations of storage- and peripheral-blocks in a…
G11C 7/18
Arrangements for writing information into, or reading information out from, a digital store: bit line organisation; Bit line lay-out

Memory device and manufacturing method of the same

Life of this patent

Memory device and manufacturing method of the same

Life of this patent

Abstract

Claims20