Memory device and method of testing the memory device for failure

A memory device comprising:

• a first chip including a memory cell array;
• and
• a second chip overlapping with the first chip by bonding to the first chip, wherein the second chip includes:
• a semiconductor substrate including a peripheral circuit area and a lower test area;
• a plurality of sub-test pads and an input pad, disposed on the lower test area of the semiconductor substrate and spaced apart from each other;
• a plurality of sub-test circuits respectively connected to the plurality of sub-test pads;
• and
• a detection circuit connected to a plurality of terminals of the plurality of sub-test circuits, the detection circuit being configured to output a detection signal changed according to a plurality of signals input from the plurality of terminals,
• wherein the first chip includes an upper test pad overlapping with a portion of the lower test area of the semiconductor substrate,
• wherein the upper test pad is bonded and connected to the input pad and any one of the plurality of sub-test pads, and
• wherein the detection circuit outputs the detection signal according to the plurality of signals changed according to which sub-test pad, among the plurality of sub-test pads, the upper test pad is bonded and connected to.