Memory interface circuitry and built-in self-testing method

A built-in self-testing method for a memory interface circuitry, wherein the memory interface circuitry comprises a clock generator, a state machine, a data pattern generator, a read register, an input/output (I/O) interface, a write register and a comparator, and the built-in self-testing method comprises:

• performing a clock signal converting step comprising configuring the clock generator to receive a first clock signal and convert the first clock signal into a second clock signal;
• performing a test signal generating step comprising configuring the state machine to generate a test signal according to the second clock signal;
• performing a data pattern generating step comprising configuring the data pattern generator to generate a data pattern according to the test signal, wherein the data pattern comprises a plurality of pre-defined data;
• performing a data transferring step comprising configuring the read register to receive the plurality of pre-defined data from the data pattern generator and sequentially output the plurality of pre-defined data to the I/O interface, wherein the I/O interface comprises an I/O buffer;
• performing a data capturing step comprising configuring the I/O buffer to capture a plurality of data from the plurality of pre-defined data according to a write strobe signal, and then to store the plurality of data in the write register;
• and
• performing a data comparing step comprising configuring the comparator to compare the plurality of pre-defined data with the plurality of data to generate a test result, wherein the test result is configured to verify an operation of the I/O interface.

A memory interface circuitry, comprising:

• a clock generator receiving a first clock signal and converting the first clock signal into a second clock signal;
• a state machine coupled to the clock generator and generating a test signal according to the second clock signal;
• a data pattern generator coupled to the state machine and generating a data pattern according to the test signal, wherein the data pattern comprises a plurality of pre-defined data;
• a register module coupled to the data pattern generator, wherein the register module receives and stores the plurality of pre-defined data;
• an input/output (I/O) interface coupled to the register module and receiving the plurality of pre-defined data from the register module, wherein the I/O interface comprises an I/O buffer, the I/O buffer captures a plurality of data from the plurality of pre-defined data according to a write strobe signal, and the plurality of data are stored into the register module;
• and
• a comparator coupled to the data pattern generator and the register module, wherein the comparator compares the plurality of pre-defined data with the plurality of data to generate a test result, and the test result is configured to verify an operation of the I/O interface.