Shift register unit and driving method therefor, gate drive circuit, and display device

A method for driving a shift register unit, applied to drive a shift register unit, wherein the shift register comprises:

• an input circuit coupled to an input signal terminal, an input control terminal, a first power supply terminal, a reference node, and a first node, wherein the input circuit is configured to transmit a first power signal provided by the first power supply terminal to the reference node in response to an input signal provided by the input signal terminal and an input control signal provided by the input control terminal, and transmit the first power signal to the first node in response to the input signal;
• a compensation control circuit coupled to a first clock signal terminal, the reference node, and the first node, wherein the compensation control circuit is configured to adjust a potential of the first node based on a potential of the reference node in response to a first clock signal provided by the first clock signal terminal;
• and
• an output circuit coupled to the first node, a second clock signal terminal, and an output terminal, wherein the output circuit is configured to transmit a second clock signal provided by the second clock signal terminal to the output terminal in response to the potential of the first node,
• wherein the input circuit comprises a first input sub-circuit, and the first input sub-circuit comprises a first input transistor and a second input transistor, wherein a gate of the first input transistor is coupled to the input signal terminal, a first electrode of the first input transistor is coupled to the first power supply terminal, and a second electrode of the first input transistor is coupled to a first electrode of the second input transistor;
• and a gate of the second input transistor is coupled to the input control terminal, and a second electrode of the second input transistor is coupled to the reference node;
• and the first input sub-circuit is configured to transmit the first power signal to the reference node in response to the input signal and the input control signal, and
• the method comprises:
• in an input period, transmitting, by the input circuit, the first power signal provided by the first power supply terminal to the reference node in response to the input signal provided by the input signal terminal and the input control signal provided by the input control terminal, and transmitting, by the input circuit, the first power signal to the first node in response to the input signal, wherein a potential of the input signal, a potential of the input control signal, and a potential of the first power signal are all a first potential;
• in an output period, transmitting, by the output circuit, the second clock signal provided by the second clock signal terminal to the output terminal in response to the potential of the first node, wherein the potential of the first node is the first potential;
• and
• in a compensation control period, adjusting, by the compensation control circuit, the potential of the first node based on the potential of the reference node in response to the first clock signal provided by the first clock signal terminal, wherein a potential of the first clock signal is the first potential;
• wherein the input period and the output period are performed in a display stage, and the compensation control period is performed in a blanking stage.

A gate drive circuit, comprising at least two cascaded shift register units, wherein the shift register comprises:

• an input circuit coupled to an input signal terminal, an input control terminal, a first power supply terminal, a reference node, and a first node, wherein the input circuit is configured to transmit a first power signal provided by the first power supply terminal to the reference node in response to an input signal provided by the input signal terminal and an input control signal provided by the input control terminal, and transmit the first power signal to the first node in response to the input signal;
• a compensation control circuit coupled to a first clock signal terminal, the reference node, and the first node, wherein the compensation control circuit is configured to adjust a potential of the first node based on a potential of the reference node in response to a first clock signal provided by the first clock signal terminal;
• and
• an output circuit coupled to the first node, a second clock signal terminal, and an output terminal, wherein the output circuit is configured to transmit a second clock signal provided by the second clock signal terminal to the output terminal in response to the potential of the first node,
• wherein the input circuit comprises a first input sub-circuit, and the first input sub-circuit comprises a first input transistor and a second input transistor, wherein a gate of the first input transistor is coupled to the input signal terminal, a first electrode of the first input transistor is coupled to the first power supply terminal, and a second electrode of the first input transistor is coupled to a first electrode of the second input transistor;
• and a gate of the second input transistor is coupled to the input control terminal, and a second electrode of the second input transistor is coupled to the reference node;
• and the first input sub-circuit is configured to transmit the first power signal to the reference node in response to the input signal and the input control signal.