Back to results
US 12,183,408 B2Granted
Operating a memory unit using a low-power direct-current (DC) power source
AssigneeNingbo Aura Semiconductor Co., Limited
InventorsArnold J D'Souza, Shyam Somayajula
Life of this patent
Estimating the term…
Abstract
Operating a memory unit using a low-power DC source. The low-power DC source provides lesser power than that required to operate the memory unit. In an embodiment, charge from the low-power source is stored on a charge storage device in a first time interval. The memory unit is operated using the charge storage device as a second power source in a second time interval. A portion of one of the first time interval and the second time interval does not overlap with the other one of the first time interval and the second time interval.
Claims20
A method performed associated with a memory unit, said method comprising:
- storing charge from a first power source on a charge storage device in a first time interval, wherein said first power source provides lesser power than that required to operate said memory unit;
- and
- operating, using said charge storage device as a second power source, said memory unit in a second time interval,
- wherein a portion of one of said first time interval and said second time interval does not overlap with the other one of said first time interval and said second time interval,
- reading, from said memory unit, a first bit in a first read duration and a second bit in a second read duration, wherein said first read duration is separated from said second read duration by an idle duration,
- wherein said idle duration comprises said first time interval, and said first read duration comprises said second time interval.
3 more elements
A device comprising:
- a charge storage unit;
- a charge pump, wherein an input of said charge pump is coupled to a first power source, an output node of said charge pump being coupled to said charge storage unit,
- wherein said first power source provides lesser power than that required to operate a memory unit,
- wherein said charge pump is designed to store charge from said first power source on said charge storage device in a first time interval,
- wherein said memory unit is operated in a second time interval using said charge storage device as a second power source,
- wherein a portion of one of said first time interval and said second time interval does not overlap with the other one of said first time interval and said second time interval;
- and
- a digital unit comprising one or more circuits to read, from said memory unit, a first bit in a first read duration and a second bit in a second read duration, wherein said first read duration is separated from said second read duration by an idle duration,
- wherein said idle duration comprises said first time interval, and said first read duration comprises said second time interval.
6 more elements
A system comprising:
- a power terminal coupled to a first power source;
- and
- a power supply unit coupled to receive power from said power terminal, said power supply unit comprising a first linear voltage regulator and a first DC-DC converter, said first DC-DC converter representing a third power source coupled to said power terminal, said first linear voltage regulator coupled to said third power source to generate a first lower supply voltage,
- wherein said first linear voltage regulator comprises:
- a core function block, said core function block comprising circuitry for generation of said first lower supply voltage;
- a charge storage unit;
- a charge pump, wherein an input of said charge pump is coupled to said third power source, an output node of said charge pump being coupled to said charge storage unit,
- wherein said third power source provides lesser power than that required to operate a memory unit,
- wherein said charge pump is designed to store charge from said power terminal on said charge storage device in a first time interval,
- wherein said memory unit is operated in a second time interval using said charge storage device as a second power source,
- wherein a portion of one of said first time interval and said second time interval does not overlap with the other one of said first time interval and said second time interval;
- and
- a digital unit comprising one or more circuits to read, from said memory unit, a first bit in a first read duration and a second bit in a second read duration, wherein said first read duration is separated from said second read duration by an idle duration,
- wherein said idle duration comprises said first time interval, and said first read duration comprises said second time interval.
11 more elements
Dependencies are inferred from the claim text.