Clock signal return scheme for data read in page buffer of memory device
AssigneeYangtze Memory Technologies Co., Ltd.
InventorShu Xie
Life of this patent
Estimating the term…
Abstract
In certain aspects, a memory device includes a memory cell array and a peripheral circuit coupled to the memory cell array. The peripheral circuit includes frequency dividers and a clock path coupled to the frequency dividers. Each of the frequency dividers is configured to receive a clock signal and generate a clock return signal. The clock return signal corresponds to the clock signal. A period of the clock return signal is greater than the period of the clock signal. The clock path is configured to merge the clock return signals.
Claims20
A memory device, comprising:
- a memory cell array;
- and
- a peripheral circuit coupled to the memory cell array the peripheral circuit comprising:
- frequency dividers, each of the frequency dividers being configured to receive a clock signal and generate a clock return signal, the clock return signal corresponding to the clock signal, a period of the clock return signal being greater than the period of the clock signal;
- a first clock level set module coupled to one of the frequency dividers, and configured to determine the clock return signal based on an address associated with the clock signal;
- and
- a clock path coupled to the frequency dividers and configured to merge the clock return signals.
A system, comprising:
- a memory device comprising a memory cell array, and a peripheral circuit coupled to the memory cell array, the peripheral circuit comprising:
- frequency dividers, each of the frequency dividers being configured to receive a clock signal and generate a clock return signal, the clock return signal corresponding to the clock signal, a period of the clock return signal is greater than the period of the clock signal;
- a first clock level set module coupled to one of the frequency dividers, and configured to determine the clock return signal based on an address associated with the clock signal;
- and
- a clock path coupled to the frequency dividers and configured to merge the clock return signals.
A method for operating a memory device, the method comprising:
- receiving a first clock signal of clock signals;
- generating a first clock return signal of clock return signals corresponding to the first clock signal, wherein a period of the first clock return signal is greater than the period of the first clock signal;
- receiving a read instruction;
- obtaining an address in the read instruction;
- and
- setting a start level of the first clock return signal based on the address.
Dependencies are inferred from the claim text.