Three-dimensional memory device and improved methods of reading the same by shortening read times

A method for reading a memory device that includes memory cells each having two or more data states, the method comprising:

• performing a first read operation, comprising:
• applying a first bit line voltage to a first selected bit line;
• and
• applying a first read voltage to a word line to determine whether a first selected memory cell coupled to the word line and the first selected bit line is at a first data state;
• and
• performing a second read operation, comprising:
• maintaining the first bit line voltage at the first selected bit line associated with the first selected memory cell which is determined to be at the first data state;
• applying a second read voltage to the word line while maintaining the first bit line voltage at the first selected bit line to determine whether a second selected memory cell coupled to the word line is at a second data state;
• and
• applying a second bit line voltage to a second selected bit line associated with the second selected memory cell, wherein the second bit line voltage is higher than the first bit line voltage.

A three-dimensional (3D) memory device, comprising:

• memory cells each configured to have two or more data states and addressable through a word line and a bit line;
• a page buffer for sensing a voltage level of a respective bit line;
• and
• a control circuit configured to:
• apply a first bit line voltage to a first selected bit line;
• apply a second bit line voltage to a second selected bit line, wherein the second bit line voltage is different from the first bit line voltage;
• apply a first read voltage to the word line to determine whether a first selected memory cell coupled to the word line and the first selected bit line is at a first data state;
• in response to the first selected memory cell being at the first data state, maintain the first bit line voltage at the first selected bit line;
• and
• apply a second read voltage to the word line while the first bit line voltage is maintained at the first selected bit line to determine whether a second selected memory cell coupled to the word line and the second selected bit line is at a second data state.