Semiconductor storage device

A device comprising:

• a first substrate having a first active region;
• a second substrate having a second active region, the second substrate provided above the first substrate in a first direction orthogonal to a surface of the first substrate;
• a first memory cell transistor provided between the first substrate and the second substrate in the first direction;
• a second memory cell transistor provided between the first substrate and the second substrate in the first direction;
• a first contact provided between the first memory cell transistor and the second memory cell transistor in a second direction perpendicular to the first direction;
• a first word line electrically connected to a gate of the first memory cell transistor;
• a first transistor having a channel region in the first active region, the first transistor configured to control supply of a voltage to the first memory cell transistor through the first contact and the first word line;
• a first bit line electrically connected to a drain of the first memory cell transistor;
• and
• a sense amplifier provided on the second substrate and electrically connected to the first bit line, the sense amplifier configured to control supply of a voltage from the sense amplifier to the drain of the first memory cell transistor through the first bit line, wherein
• the first substrate, the first memory cell transistor, the second memory cell transistor, the first word line, the first bit line, and the sense amplifier are provided in a first chip, and
• the second substrate and the first transistor are provided in a second chip.

A storage device comprising

• a first substrate having a first active region;
• a second substrate having a second active region, the second substrate provided above the first substrate in a first direction orthogonal to a surface of the first substrate;
• a first memory cell transistor provided between the first substrate and the second substrate in the first direction;
• a first word line electrically connected to a gate of the first memory cell transistor;
• a first bit line electrically connected to a drain of the first memory cell transistor;
• a first transistor having a channel region in the first active region, the first transistor configured to control supply of a voltage to the gate of the first memory cell transistor through the first word line;
• a sense amplifier having a channel region in the second active region, the sense amplifier configured to control supply of a voltage to the drain of the first memory cell transistor through the first bit line;
• and
• a capacitor provided adjacent to the first transistor in a second direction perpendicular to the first direction.