Memory circuits and devices, and methods thereof
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYih Wang, Tung-Cheng Chang, Perng-Fei Yuh, Gu-Huan Li, Chia-En Huang, Chun-Ying Lee
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Abstract
A memory circuit includes a plurality of bitcells coupled to a plurality of bitlines, a plurality of wordlines, a plurality of source lines, and a control line. A first of the bitcells and a second of the bitcells are coupled to a first of the bitlines. The first bitcell is coupled to a first of the source lines. The second bitcell is coupled to a second of the source lines. The first source line is different from the second source line.
Claims20
A memory circuit, comprising:
- a plurality of bitcells coupled to a plurality of bitlines, a plurality of wordlines, a plurality of source lines, and a control line;
- wherein:
- a first of the bitcells and a second of the bitcells are coupled to a first of the bitlines;
- the first bitcell is separately coupled to a first of the source lines and the control line;
- and
- the second bitcell is separately coupled to a second of the source lines and the control line;
- wherein:
- the first source line is different from the second source line;
- the first bitcell comprises a first transistor;
- the second bitcell comprises a second transistor;
- and
- the first transistor is coupled to the second transistor through a connection line, the connection line configured to float.
A memory device, comprising:
- a plurality of bitcells coupled to a bitline, a plurality of wordlines, a plurality of source lines, and a control line;
- wherein:
- ones of the plurality of bitcells are coupled to one of the source lines and separately coupled to the control line;
- and
- the one of the source lines is configured for a source-line signal of a voltage level higher than a ground level of voltage,
- wherein:
- a first one of the plurality of bitcells comprises a first transistor;
- a second one of the plurality of bitcells comprises a second transistor;
- and
- the first transistor is coupled to the second transistor through a connection line, wherein the connection line is not the bitline and is configured to float.
A method for a memory circuit, wherein the memory circuit comprises a bitcell, the bitcell comprises a first transistor and a second transistor, and a drain of the first transistor is coupled to a source of the second transistor, the method comprising:
- supplying a first signal of a first voltage level to a gate of the first transistor, the first voltage level to switch off the first transistor;
- supplying a second signal of a second voltage level to a gate of the second transistor, the second voltage level to switch off the second transistor;
- and
- supplying, from a source line, a third signal of a third voltage level to a connection point between the drain of the first transistor and the source of the second transistor, the third voltage level being higher than a ground level of voltage.
Dependencies are inferred from the claim text.