Memory array structures and methods of forming memory array structures

A memory array structure, comprising:

• a first block of memory cells including a first plurality of local access lines, wherein each local access line of the first plurality of local access lines is connected to control gates of a respective plurality of memory cells of the first block of memory cells, and wherein each local access line of the first plurality of local access lines is selectively connected to a respective global access line of a plurality of global access lines through a respective selective connection of a first plurality of selective connections;
• a second block of memory cells including a second plurality of local access lines, wherein each local access line of the second plurality of local access lines is connected to control gates of a respective plurality of memory cells of the second block of memory cells, and wherein each local access line of the second plurality of local access lines is selectively connected to the respective global access line of a corresponding local access line of the first plurality of local access lines through a respective selective connection of a second plurality of selective connections;
• and
• a current path as a direct electrical connection between a particular local access line of the first plurality of local access lines and its corresponding local access line of the second plurality of local access lines;
• wherein the first plurality of selective connections are selectively activated independently from the second plurality of selective connections.

A memory array structure, comprising:

• a first block of memory cells including a first plurality of local access lines, wherein each local access line of the first plurality of local access lines is connected to control gates of a respective plurality of memory cells of the first block of memory cells;
• a second block of memory cells including a second plurality of local access lines, wherein each local access line of the second plurality of local access lines is connected to control gates of a respective plurality of memory cells of the second block of memory cells, and wherein each local access line of the second plurality of local access lines is in a same physical plane as a corresponding local access line of the first plurality of local access lines;
• a current path between a particular local access line of the first plurality of local access lines and its corresponding local access line of the second plurality of local access lines;
• and
• a conductive plate having an isolation region extending less than a full length of the conductive plate;
• wherein the particular local access line of the first plurality of local access lines comprises a first portion of the conductive plate on a first side of the isolation region, and wherein its corresponding local access line of the second plurality of local access lines comprises a second portion of the conductive plate on a second side of the isolation region;
• and
• wherein the current path comprises a third portion of the conductive plate between an end of the isolation region and an edge of the conductive plate.

A method of forming a memory array structure, comprising:

• forming a first conductive plate;
• forming a second conductive plate overlying the first conductive plate;
• forming a first isolation region in the first conductive plate and extending less than a full length of the first conductive plate;
• forming a second isolation region in the second conductive plate and extending less than a full length of the second conductive plate;
• forming a first contact connected to the first conductive plate on a first side of the first isolation region;
• forming a second contact connected to the first conductive plate on a second side of the first isolation region;
• forming a third contact connected to the second conductive plate on a first side of the second isolation region;
• forming a fourth contact connected to the second conductive plate on a second side of the second isolation region;
• and
• forming a conductor connected to the third contact and connected to the second contact;
• wherein the first conductive plate forms control gates of a first plurality of memory cells of a first block of memory cells and forms control gates of a first plurality of memory cells of a second block of memory cells;
• and
• wherein the second conductive plate forms control gates of a second plurality of memory cells of the first block of memory cells and forms control gates of a second plurality of memory cells of the second block of memory cells.