Back to results
US 12,183,393 B2Granted
High-speed multi-port memory supporting collision
AssigneeQUALCOMM Incorporated
InventorsPradeep Raj, Rahul Sahu, Sharad Kumar Gupta
Life of this patent
Estimating the term…
Abstract
A multi-port memory is provided that supports collision between a read port and a write port to the same multi-port bitcell. A sense amplifier reads a data bit from a multi-port bitcell when a write port to the multi-port bitcell is addressed during a system clock signal. Should a read port to the multi-port bitcell be addressed during the same system clock signal, a multiplexer selects for an output bit from the sense amplifier.
Claims9
A multi-port memory, comprising:
- a multi-port bitcell including a first read port having a first read port bit line and a first read port word line, the multi-port bitcell further including a write port having a pair of write bit lines;
- an address comparator configured to detect a collision responsive to a write port address being directed to the write port and a read port address being directed to the first read port;
- a read port word line controller configured to assert the first read port word line responsive to a lack of a detection of the collision and configured to not assert the first read port word line responsive to a detection of the collision;
- a sense amplifier configured to perform a differential read through the write port responsive to the write port address being directed to the write port;
- an inverter coupled to the first read port bit line;
- and
- a multiplexer configured to select between an output of the inverter and the sense amplifier.
4 more elements
A multi-port memory, comprising:
- an address comparator configured to detect a collision responsive to a read port address and a write port address both being directed to a first multi-port bitcell;
- a sense amplifier configured to read a first data bit from the first multi-port bitcell through a write port;
- a write driver configured to write a second data bit to the first multi-port bitcell through the write port after a completion of the read of the first data bit;
- a multiplexer coupled to the sense amplifier, the multiplexer configured to select for the first data bit responsive to a detection of the collision;
- and
- an inverter coupled to a read port bit line in a first read port in the first multi-port bitcell, wherein the multiplexer is further configured to select for an output of the inverter responsive to a detection of a lack of the collision.
3 more elements
Dependencies are inferred from the claim text.