Memory device data loss prevention

A memory device, comprising:

• a memory core including a plurality of capacitor-based memory cells;
• and
• control logic, the control logic including registers and counters, wherein the control logic is operable in a first mode and a second mode, and is configured to:
• receive a first active command and a first row address from an external device;
• activate memory cells corresponding to the first row address, from among the plurality of memory cells, in response to the first active command;
• in the first mode:
• record the first row address in one of the registers, count an activation count of the first row address using a first counter of the counters, and
• count a lifetime count of the first row address using a second counter of the counters;
• and
• in the second mode:
• record the first row address in one of the registers, and
• count the activation count of the first row address using the first counter of the counters.

An operating method of a memory device that includes memory cells and registers configured to record row addresses, the method comprising:

• receiving, at the memory device, an active command and a first row address from an external device;
• when row addresses are recorded in all the registers, evicting a second row address, which has a lifetime count of “0” and has a smallest activation count, from among row addresses recorded in the registers;
• and
• storing, at the memory device, the first row address in an empty register of the registers, increasing an activation count of the first row address, and increasing a lifetime count of the first row address.