Logical operations using memory cells

A method, comprising:

• performing a logical operation by:
• charging, to a first voltage, a read digit line coupled to a plurality of memory cells associated with a memory device, wherein each one of the memory cells of the plurality of memory cells stores a data value corresponding to a respective input of the logical operation;
• activating, after charging the read digit line, a plurality of read word lines corresponding to the plurality of memory cells;
• enabling a sense amplifier coupled to the read digit line;
• and
• sensing, via the sense amplifier, a result of the logical operation, wherein:
• the result of the logical operation is a logic 0 value responsive to the read digit having a second voltage that is less than the first voltage after activating the plurality of read word lines, wherein the read digit line transitions from the first voltage to the second voltage based on at least one of the plurality of memory cells storing a first data value corresponding to a logic 1 value;
• or
• the result of the logical operation is the logic 1 value responsive to the read digit line having the first voltage after activating the plurality of read word lines, wherein the read digit line maintains the first voltage based on all of the plurality of memory cells storing a second data value corresponding to the logic 0 value;
• and
• writing the result of the logical operation or a complement of the result of the logical operation to memory cells coupled to a write digit line of the memory device based on enabling a first transistor coupled to the sense amplifier or enabling a second transistor coupled to the sense amplifier.

An apparatus, comprising:

• an array of memory cells;
• and
• a controller coupled to the array of memory cells, wherein the controller is configured to cause performance of a multi-input logical operation by:
• charging, to a first voltage, a read digit line coupled to a plurality of memory cells, wherein each one of the plurality of memory cells stores a data value corresponding to a respective one of the inputs;
• activating, after charging the read digit line, a plurality of read word lines corresponding to the plurality of memory cells;
• enabling a sense amplifier coupled to the read digit line;
• and
• controlling the sense amplifier to sense a result of the logical operation, wherein:
• the result of the logical operation is a logic 0 value responsive to the read digit having a second voltage that is less than the first voltage after activating the plurality of read word lines, wherein the read digit line transitions from the first voltage to the second voltage based on at least one of the plurality of memory cells storing a first data value corresponding to a logic 1 value;
• or
• the result of the logical operation is the logic 1 value responsive to the read digit line having the first voltage after activating the plurality of read word lines, wherein the read digit line maintains the first voltage based on all of the plurality of memory cells storing a second data value corresponding to the logic 0 value;
• and
• enable a first transistor coupled to the sense amplifier to write the result of the multi-input logical operation to memory cells coupled to a first write row line and enable a second transistor coupled to the sense amplifier to write a complement of the result of the multi-input logical operation to memory cells coupled to a second write row line.