Information processing apparatus, information processing system, and semiconductor storage device

An information processing system comprising a host device and a semiconductor storage device capable of being placed into the host device, wherein

• the semiconductor storage device comprises:
• a housing having a first surface, a second surface located on a side opposite to the first surface, a first end edge extending in a first direction, a second end edge located on a side opposite to the first end edge and extending in the first direction, a first side edge extending in a second direction intersecting the first direction, and a first corner portion being between the first end edge and the first side edge;
• a nonvolatile memory;
• a controller being connected to the nonvolatile memory;
• and
• a plurality of terminals provided on the first surface,
• the plurality of terminals of the semiconductor storage device include a first plurality of terminals, a second plurality of terminals, and a third plurality of terminals,
• the first plurality of terminals are arranged in the first direction at a position closer to the first end edge than the second end edge,
• the third plurality of terminals are arranged in the first direction at a position closer to the second end edge than the first end edge,
• the second plurality of terminals are arranged between the first plurality of terminals and the third plurality of terminals in the first direction,
• the first plurality of terminals are closer to the first end edge than the second plurality of terminals are,
• the first plurality of terminals include at least one pair of first signal terminals for differential data signals, the differential data signals complying with PCIe standard,
• the first plurality of terminals include a first plurality of ground terminals assigned to ground,
• each pair of the at least one pair of first signal terminals is located between two of the first plurality of ground terminals,
• the second plurality of terminals include a second plurality of ground terminals assigned to ground,
• the third plurality of terminals include differential clock signal terminals assigned to differential clock signals having a frequency lower than that of the differential data signals, a first and second terminals, each of the first and the second terminals being assigned to a single-end signal, a first power supply terminal assigned to a first power supply, and a second power supply terminal assigned to a second power supply having a voltage equal to or lower than that of the first power supply,
• the host device has a connector into which the semiconductor storage device is capable of being placed, and
• the host device is configured to
• supply the first power supply to the first power supply terminal,
• supply the second power supply to the second power supply terminal,
• supply a reference clock signal to the differential clock signal terminals, when a clock request signal from the first terminal is Low after a period since the first power supply and second power supply are supplied to the semiconductor storage device reaches a first time, and
• supply a High signal to the second terminal after a period since the reference clock signal are supplied reaches a second time.