Clock recovery circuit

A video receiver, comprising:

• a link symbol extractor circuit configured to receive video data and a link clock signal, assert a link-data-enable signal during an active period in response to packets of valid link symbols in the video data, each packet including a subset of the valid link symbols, and assert, during a blanking period, a link-data-enable-blanking signal for a period derived from a count of the valid link symbols per packet during the active period;
• a link-to-pixel mapper circuit clocked by the link clock signal to convert the valid link symbols to active pixels in response to the link-data-enable signal, and convert dummy link symbols in the video data to dummy pixels in response to the link-data-enable-blanking signal, the link-to-pixel mapper circuit clocked by a reference clock signal to provide the active pixels and the dummy pixels;
• a timing generator circuit configured to assert a video-enable-active signal in response to availability of the active pixels and assert a video-enable-blanking signal in response to availability of the dummy pixels;
• an OR logic circuit configured to assert a video-clock-enable signal in response to either the video-enable-active signal or the video-enable-blanking signal being asserted;
• and
• a clock buffer circuit having a clock-in port coupled to input the reference clock signal and an enable port coupled to input the video-clock-enable signal and configured to generate a video pixel clock signal having pulses of the reference clock signal as enabled by the video-clock-enable signal.