Pixel circuit, display panel, and display device

A pixel circuit, comprising:

• a semiconductor layer on a side of a base substrate, wherein the semiconductor layer is configured to form an active layer of each of various transistors in the pixel circuit, the active layer comprising a channel region, and a source electrode region and a drain electrode region that are disposed on both sides of the channel region;
• a first metal layer on the side of the base substrate, wherein the first metal layer is configured to form a gate electrode of the transistor and a first capacitive electrode of a storage capacitor in the pixel circuit, an overlap region being present between the gate electrode of the transistor and the channel region;
• and
• a second metal layer on the side of the base substrate, wherein the second metal layer is configured to form a second capacitive electrode of the storage capacitor, the second capacitive electrode being at least partially overlapped with the first capacitive electrode, and the second capacitive electrode being coupled to a drive power line extending along a first direction;
• wherein the gate electrodes of the transistors and the storage capacitor are arranged in sequence along the first direction;
• the second capacitive electrodes of each two adjacent pixel circuits are coupled via a connection portion along a second direction, wherein the connection portion is disposed on the same layer as the second metal layer, the connection portion is parallel to the channel region of at least one of the various transistors, and the connection portion is overlapped with a data signal line extending along the first direction, the first direction being perpendicular to the second direction;
• in the various transistors, a gate electrode of a light-emitting control transistor is disposed between a gate electrode of a reset transistor and a gate electrode of a data write transistor;
• wherein the data write transistor comprises a first data write transistor and a second data write transistor;
• the reset transistor comprises a first reset transistor and a second reset transistor;
• and the light-emitting control transistor comprises a first light-emitting control transistor and a second light-emitting control transistor;
• wherein
• a drain electrode region of the first data write transistor is coupled to a drain electrode region of a drive transistor in each of the transistors, and a source electrode region of the first data write transistor is coupled to a gate electrode of the drive transistor;
• a drain electrode region of the second data write transistor is coupled to a source electrode region of the drive transistor, and a source electrode region of the second data write transistor is coupled to the data signal line;
• and both a gate electrode of the first data write transistor and a gate electrode of the second data write transistor are coupled to a gate electrode drive line;
• both a source electrode region of the first reset transistor and a source electrode region of the second reset transistor are coupled to a reset signal line;
• both a gate electrode of the first reset transistor and a gate electrode of the second reset transistor are coupled to a reset control line;
• a drain electrode region of the first reset transistor is coupled to the gate electrode of the drive transistor in each of the transistors, and a drain electrode region of the second reset transistor is coupled to an anode of a light-emitting element;
• and
• a drain electrode region of the first light-emitting control transistor is coupled to the source electrode region of the drive transistor, and a source electrode region of the first light-emitting control transistor is coupled to the drive power line;
• a drain electrode region of the second light-emitting control transistor is coupled to the anode of the light-emitting element, a source electrode region of the second light-emitting control transistor is coupled to the drain electrode region of the drive transistor, and both a gate electrode of the first light-emitting control transistor and a gate electrode of the second light-emitting control transistor are coupled to a light-emitting control line;
• and the second metal layer comprises a first metal pattern and a second metal pattern;
• wherein the first metal pattern is configured to form the second capacitive electrode, and the second metal pattern is partially overlapped with an active layer of the first data write transistor.