A pixel compensation circuit, comprising a first transistor, a driving transistor, a compensation transistor, a second transistor, a third transistor, a reset transistor, a storage capacitor, and a light-emitting device;
- wherein a gate of the first transistor is electrically connected to a second scanning line, a source of the first transistor is electrically connected to a data line, and a drain of the first transistor is electrically connected to a first node, wherein the second scanning line is configured to provide a second scanning signal, and the data line is configured to provide a data signal;
- wherein a gate of the driving transistor is electrically connected to a third node, a source of the driving transistor is electrically connected to a second node, and a drain of the driving transistor is electrically connected to the first node;
- wherein a gate of the compensation transistor is electrically connected to a first scanning line, a source of the compensation transistor is electrically connected to the second node, and a drain of the compensation transistor is electrically connected to the third node, wherein the first scanning line is configured to provide a first scanning signal;
- wherein a gate of the second transistor is electrically connected to the second scanning line, a source of the second transistor is electrically connected to the second node, and a drain of the second transistor is electrically connected to a positive electrode of a power supply;
- wherein a gate of the third transistor is electrically connected to the first scanning line, a source of the third transistor is electrically connected to the first node, and a drain of the third transistor is electrically connected to the light-emitting device at a fourth node, wherein another end of the light-emitting device is electrically connected to a negative electrode of the power supply;
- wherein a gate of the reset transistor is electrically connected to the first scanning line at a fifth node, the storage capacitor is electrically connected between a source of the reset transistor and the third node, a source of the reset transistor is electrically connected to the fourth node through a wire, and a drain of the reset transistor is electrically connected to a reset signal line;
- and
- wherein the first transistor, the compensation transistor, and the reset transistor are unipolar transistors which have a type complementary to a type of the driving transistor, the second transistor, and the third transistor;
- wherein the first scanning line and the second scanning line are combined to correspond to a reset phase, a data writing phase, and a light-emitting phase sequentially;
- wherein in the reset phase, the first scanning line is at a low level and the second scanning line is at a high level;
- in the data writing phase, both the first scanning line and the second scanning line are at a low level;
- in the light-emitting phase, both the first scanning line and the second scanning line are at a high level.