System on a chip with deep learning accelerator and random access memory

A method, comprising:

• storing, in random access memory of a device having a first integrated circuit die having at least one processing unit operable to execute first instructions having matrix operands, a second integrated circuit die having the random access memory, and a third integrated circuit die having a central processing unit:
• first data representative of matrices of an artificial neural network;
• second data representative of the first instructions;
• and
• third data representative of an application programmed with second instructions executable by the central processing unit;
• executing, by the at least one processing unit, the first instructions to implement computations of the artificial neural network to generate an output;
• and
• executing, by the central processing unit, the second instructions to process the output as an input to the application;
• wherein the first integrated circuit die further includes a local memory and a control unit configured to control execution of the first instructions by the at least one processing unit.

An apparatus, comprising:

• a peripheral bus;
• and
• a system on a chip, having:
• an interface connected to the peripheral bus;
• a first integrated circuit die having at least one processing unit operable to execute instructions having matrix operands;
• a second integrated circuit die having random access memory, wherein the random access memory is configured to store:
• first data representative of matrices of an artificial neural network;
• and
• second data representative of the instructions executable by the at least one processing unit to implement computations of the artificial neural network;
• a third integrated circuit die having a central processing unit;
• and
• an integrated circuit package configured to enclose the first integrated circuit die, the second integrated circuit die, and the third integrated circuit die.