Fine-grained sparsity computations in systolic array

An integrated circuit device comprising:

• an array of processing elements arranged in rows and columns, wherein each processing element includes:
• a register configured to store a value;
• a multiplexor configured to select, based on metadata associated with the value stored in the register, an input element from a plurality of input data buses;
• a multiplier configured to multiply the selected input element with the value stored in the register to generate a multiplication result;
• and
• an adder configured to add the multiplication result to a partial sum input to generate a partial sum output,
• wherein the array of processing elements is operable in a sparsity mode of operation and a normal mode of operation.

A method for operating an acceleration circuit having an array of processing elements arranged in rows and columns to perform a matrix multiplication operation, the method comprising:

• receiving, by a processing element in the array of processing elements, a value for storing in a register;
• storing, by the processing element, the value in the register;
• receiving, by the processing element, a set of input elements on respective input data buses;
• selecting, by a multiplexer of the processing element, an input element from the input data buses based on metadata associated with the value stored in the register;
• multiplying, by a multiplier of the processing element, the selected input element with the value stored in the register to generate a multiplication result;
• and
• adding, by an adder of the processing element, the multiplication result to a partial sum input to generate a partial sum output,
• wherein the array of processing elements is operable in a sparsity mode of operations and a normal mode of operation.