Neural network operation method and apparatus based on a chip having an operation array

An operation apparatus based on a chip having an operation array, the apparatus being connected to the operation array, the operation array comprising K rows of operation units, the apparatus comprising a circuitry configured to:

• obtain a neural network model, the neural network model comprising D neural network layers, each neural network layer corresponding to M rows and N columns of neurons;
• determine, from M*N*D pieces of neurons of the D neural network layers, K neurons to be operated corresponding to each operation clock cycle, sort the K neurons according to a sorting rule comprising an input data reordering algorithm, and input the K neurons to be operated, after being sorted, to the K rows of operation units of the operation array in the each operation clock cycle;
• and
• perform an operation on the inputted K neurons in the each operation clock cycle by using the operation array,
• wherein M, N, D, and K are positive integers.

A chip having an operation array, applicable to operation of a neural network model, the chip comprising:

• a storage array, a first programmable logic circuit, a second programmable logic circuit, and the operation array, the first programmable logic circuit being electrically connected to the storage array and the second programmable logic circuit, the second programmable logic circuit being electrically connected to the storage array and the operation array, the operation array comprising K rows and L columns of operation units,
• wherein:
• the storage array is configured to store the neural network model, the neural network model comprising D neural network layers, each neural network layer corresponding to M rows and N columns of neurons;
• the first programmable logic circuit is configured to obtain the neural network model to be operated;
• the second programmable logic circuit being configured to determine, from M*N*D neurons of the D neural network layers, K neurons to be operated corresponding to each operation clock cycle, sort the K neurons according to a sorting rule comprising an input data reordering algorithm, and input the K neurons to be operated after being sorted, to the K rows of operation units of the operation array in the each operation clock cycle;
• the operation array being configured to perform an operation on the inputted K neurons in the each operation clock cycle by using the operation array;
• and
• M, N, D, and K are positive integers.