Increasing performance of computational array accelerators

An integrated circuit device comprising:

• an array of processing engines having a plurality of columns each configured to generate a column output, wherein each column in the plurality of columns includes:
• a plurality of row groups each having a plurality of non-adjacent processing engines along the column, wherein each processing engine of the plurality of non-adjacent processing engines in a row group includes a computational circuit and is configured to perform operations including:
• receiving an input value for computing the column output;
• performing a computation on the input value over a plurality of clock cycles using the computational circuit to derive an intermediate value;
• and
• outputting the intermediate value from the processing engine to a next row group;
• and
• a column accumulator to accumulate intermediate values outputted from a last row group to generate the column output.

A method for computing a column output in a column of processing engines of an array, wherein the column has a series of row groups that each include a plurality of non-adjacent processing engines along the column, the method comprising:

• sequentially performing, by each row group in the series of row groups of the column:
• loading, by each processing engine of the row group, an input value for computing the column output;
• performing, by each processing engine of the row group, a computation on the input value to derive an intermediate value over a plurality of clock cycles;
• and
• outputting, by each processing engine of the row group, the intermediate value to a next row group;
• and
• accumulating intermediate values from a last row group to generate the column output.