MTJ-based hardware synapse implementation for binary and ternary deep neural networks

A method comprising:

• providing an array of synapse devices arranged in rows and columns, wherein each of said synapse devices comprises:
• first and second magnetic tunnel junction (MTJ) devices, wherein each of said MTJ devices has a fixed layer port and a free layer port, and wherein said fixed layer ports of said first and second MTJ devices are connected to each other,
• a first control circuit connected to the free layer port of said first MTJ device and configured to provide a first control signal, and
• a second control circuit connected to the free layer port of said second MTJ device and configured to provide a second control signal,
• wherein said first and second control circuits are configured to perform a gated XNOR (GXNOR) operation between synapse and activation values, and wherein an output of the GXNOR is represented by the output current through both of said first and second MTJ devices,
• wherein all of said synapse devices arranged in any one of said columns share an input voltage,
• wherein all of said synapse devices arranged in any one of said rows share said first and second control signals, and
• wherein outputs of all of said synapse devices arranged in any one of said rows are connected;
• and
• at a training stage, training said array of synapse devices by:
• (i) inputting all of said input voltages associated with each of said columns,
• (ii) setting said first and second control signals associated with each of said rows to perform said GXNOR operation, and
• (iii) calculating an output vector of said array as a weighted sum of said input voltages multiplied by a synaptic weightings matrix comprising synapse weights of all of said synapse devices in said array.

A computer memory structure comprising:

• a plurality of ternary synapse devices, each comprising:
• first and second magnetic tunnel junction (MTJ) devices, wherein each of said MTJ devices has a fixed layer port and a free layer port, and wherein said fixed layer ports of said first and second MTJ devices are connected to each other,
• a first control circuit connected to the free layer port of said first MTJ device and configured to provide a first control signal, and
• a second control circuit connected to the free layer port of said second MTJ device and configured to provide a second control signal,
• wherein said ternary synapse devices are configured to perform a gated XNOR (GXNOR) operation between a ternary synapse weight and one or more binary, or ternary activation values;
• and wherein an output of the GXNOR is represented by a sum of the output currents through both of said first and second MTJ devices.