Deep neural network accelerator using heterogeneous multiply-accumulate unit

A deep neural network accelerator using a multiply-accumulate unit, the deep neural network accelerator comprising:

• a unit array circuit comprising:
• a first operational unit and a second operational unit adjacent to each other in a column direction and having different sizes from each other based on respective sizes of hardware of the first operational unit and the second operational unit;
• and
• a third operational unit and a fourth operational unit adjacent to each other in the column direction, having different sizes from each other, and adjacent to the first operational unit and the second operational unit in a row direction;
• a first multiplexer configured to determine a path between the first operational unit and one operational unit of the third operational unit and the fourth operational unit as a first activation propagation path;
• a second multiplexer configured to determine a path between the second operational unit and the other operational unit of the third operational unit and the fourth operational unit as a second activation propagation path;
• and
• an activation propagation delay flip-flop configured to delay the first activation propagation path when the one operational unit is the third operational unit;
• and
• a timing error detector circuit configured to detect timing errors from each of the operational units,
• wherein, when supply voltage is reduced to lower power consumption by the deep neural network accelerator, computational accuracy of the deep neural network operating at the reduced supply voltage is not decreased by a timing error, as detected by the timing error detector circuit, of the multiply-accumulate unit caused by the reduction in the supply voltage.

A deep neural network accelerator using a multiply-accumulate unit, the deep neural network accelerator comprising:

• a unit array circuit comprising a plurality of operational units, the plurality of operational units including:
• a first operational unit and a second operational unit adjacent to each other in a column direction and having different sizes from each other based on respective sizes of hardware of the first operational unit and the second operational unit;
• and
• a third operational unit and a fourth operational unit adjacent to each other in the column direction, having different sizes from each other, and adjacent to the first operational unit and the second operational unit in a row direction;
• a first multiplexer configured to determine a path between the first operational unit and one operational unit of the third operational unit and the fourth operational unit as a first activation propagation path;
• a second multiplexer configured to determine a path between the second operational unit and the other operational unit of the third operational unit and the fourth operational unit as a second activation propagation path;
• and
• an activation propagation delay flip-flop configured to delay the first activation propagation path when the one operational unit is the third operational unit;
• and
• an activator circuit providing activations to the unit array circuit;
• a plurality of activation delay flip-flops configured to receive the activations from the activator circuit and delay the received activations;
• an activation propagation switching unit circuit configured to determine activation propagation paths for the operational units in the unit of four operational units based on the activations delayed by the activation delay flip-flops;
• and
• a timing error detector circuit configured to detect timing errors from each of the operational units,
• wherein, when supply voltage is reduced to lower power consumption by the deep neural network accelerator, computational accuracy of the deep neural network operating at the reduced supply voltage is not decreased by a timing error, as detected by the timing error detector circuit, of the multiply-accumulate unit caused by the reduction in the supply voltage.