Data representation for dynamic precision in neural network cores

A system comprising:

• a neural network processor comprising a plurality of neural cores, the neural network processor having one or more processor precisions per activation, the neural network processor being configured to accept data having a feature dimension;
• a transformation circuit coupled to the neural network processor, and adapted to:
• receive an input data tensor having an input precision per channel at one or more features;
• determine one of the one or more processor precisions;
• determining a number of blocks by dividing the input bit precision of the input data tensor by one of the one or more processor bit precisions;
• based on the determination of the one of the one or more processor precisions, transform the input data tensor from the input precision to the determined one of the one or more processor precisions, wherein transforming the input data tensor comprises removing one or more least significant bits of the input data tensor, wherein a number of the one or more least significant bits is based on the one or more processor bit precisions;
• divide the input data tensor into the number of blocks, each block conforming to one of the feature dimensions of the neural network processor;
• and
• provide each of the number of blocks to one of the plurality of neural cores;
• and wherein
• the neural network processor is adapted to compute, by the plurality of neural cores, output of one or more neural network layers.

A system comprising:

• a neural network processor comprising a plurality of neural cores, the neural network processor being configured for one or more feature dimensions at one or more processor bit precisions;
• and
• a transformation circuit coupled to the neural network processor, and adapted to:
• receive an input data tensor having feature dimensions at an input bit precision;
• determine one of the one or more processor bit precisions;
• determining a number of blocks by dividing the input bit precision of the input data tensor by one of the one or more processor bit precisions;
• based on the determination of the one of the one or more processor bit precisions, transform the input data tensor from the input bit precision to the determined one of the one or more processor bit precisions, wherein transforming the input data tensor comprises and removing one or more least significant bits of the input data tensor, and wherein a number of the one or more least significant bits is based on the one or more processor bit precisions;
• divide the input data tensor into the number of blocks, each block conforming to one of the feature dimensions of the neural network processor;
• and
• provide each of the number of blocks to one of the plurality of neural cores;
• and wherein the plurality of neural cores is adapted to compute output of one or more neural network layers.

A method comprising:

• receiving an input data tensor,
• the input data tensor having an input precision per channel at one or more features;
• determining a processor precision of a neural network processor;
• determining a number of blocks by dividing the input bit precision of the input data tensor by one of the one or more processor bit precisions;
• based on the determination of the processor precision, transforming the input data tensor from the input precision to the processor precision of the neural network processor, wherein transforming the input data tensor comprises removing one or more least significant bits of the input data tensor, and wherein a number of the one or more least significant bits is based on the processor precision,
• the neural network processor having a plurality of neural cores;
• the neural network processor being configured to accept data having a feature dimension;
• dividing the input data tensor into the number of blocks, each block conforming to one of the feature dimensions of the neural network processor;
• and
• providing each of the number of blocks to one of the plurality of neural cores, and wherein the neural network processor is adapted to compute, by the plurality of neural cores, output of one or more neural network layers.