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US 12,182,615 B2Granted
Mechanism to handle breakpoints in a multi-element processor
AssigneeMicron Technology, Inc.
InventorsBryan Hornung, David Patrick
Life of this patent
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Abstract
Devices and techniques for handling breakpoints in a multi-element processor are described herein. A compute node includes a hybrid threading processor and hybrid threading fabric, where the hybrid threading fabric comprises a plurality of memory-compute tiles, where each of the memory-compute tiles include respective processing and storage elements used to execute a kernel, and where each of the memory-compute tiles includes a breakpoint controller to initiate a breakpoint for the plurality of memory-compute tiles.
Claims20
A compute node comprising:
- a hybrid threading processor;
- and
- hybrid threading fabric, wherein the hybrid threading fabric comprises a plurality of memory-compute tiles, wherein each of the plurality of memory-compute tiles includes respective compute elements and storage elements used to execute a kernel, and a respective breakpoint controller configured to initiate a breakpoint for the plurality of memory-compute tiles.
An apparatus comprising:
- dispatch interface circuitry configured to communicate with a plurality of memory-compute tiles, wherein each of the plurality of memory-compute tiles includes respective compute elements and storage elements used to execute a kernel, and a respective breakpoint controller to initiate a breakpoint among the plurality of memory-compute tiles;
- wherein the dispatch interface circuitry is configured to:
- detect a breakpoint request signal that is asserted by one of the plurality of memory-compute tiles;
- and
- assert a breakpoint stop signal to the plurality of memory-compute tiles in response to detecting the breakpoint request signal.
2 more elements
A method comprising:
- detecting, at a central controller of a coarse-grained reconfigurable array (CGRA) processor, a breakpoint request signal that is asserted by one of a plurality of processing elements of the CGRA processor, wherein the central controller is configured to communicate with a plurality of processing elements, wherein each of the plurality of processing elements includes respective functional elements and storage elements used to execute a kernel, and a respective breakpoint controller to initiate a breakpoint for the plurality of processing elements;
- and
- asserting a breakpoint stop signal to the plurality of processing elements in response to detecting the breakpoint request signal.
Dependencies are inferred from the claim text.