Apparatuses, methods, and systems for a packed data convolution instruction with shift control and width control

A method comprising:

• decoding a single instruction into a decoded single instruction by a decoder circuit of a processor core, the single instruction having fields that identify a first packed data source, a second packed data source, a packed data destination, a sliding window width, and a stride, and an opcode that indicates an execution circuit is to:
• generate a first chunk of contiguous elements of the first packed data source having a width of the sliding window width,
• generate a second chunk of contiguous elements of the first packed data source having the width of the sliding window width and shifted by the stride,
• multiply each element of the first chunk by a corresponding element of a respective chunk of the second packed data source to generate a first set of products,
• add the first set of products together to generate a first sum,
• multiply each element of the second chunk by a corresponding element of a respective chunk of the second packed data source to generate a second set of products,
• add the second set of products together to generate a second sum, and
• store the first sum in a first element of the packed data destination and the second sum in a second element of the packed data destination;
• and
• executing the decoded single instruction by the execution circuit of the processor core according to the opcode.

A non-transitory machine readable medium that stores program code that when executed by a machine causes the machine to perform a method comprising:

• decoding a single instruction into a decoded single instruction by a decoder circuit of a processor core, the single instruction having fields that identify a first packed data source, a second packed data source, a packed data destination, a sliding window width, and a stride, and an opcode that indicates an execution circuit is to:
• generate a first chunk of contiguous elements of the first packed data source having a width of the sliding window width,
• generate a second chunk of contiguous elements of the first packed data source having the width of the sliding window width and shifted by the stride,
• multiply each element of the first chunk by a corresponding element of a respective chunk of the second packed data source to generate a first set of products,
• add the first set of products together to generate a first sum,
• multiply each element of the second chunk by a corresponding element of a respective chunk of the second packed data source to generate a second set of products,
• add the second set of products together to generate a second sum, and
• store the first sum in a first element of the packed data destination and the second sum in a second element of the packed data destination;
• and
• executing the decoded single instruction by the execution circuit of the processor core according to the opcode.