Systems and methods for computing dot products of nibbles in two tile operands

An apparatus comprising:

• circuitry to receive an instruction, the instruction to indicate a first matrix having M rows by K columns of 32-bit elements each having eight 4-bit data elements, a second matrix having K rows by N columns of 32-bit elements each having eight 4-bit data elements, and a third matrix having M rows by N columns, the instruction having a first indicator to indicate whether the 4-bit data elements of the first matrix are signed or unsigned, and a second indicator to indicate whether the 4-bit data elements of the second matrix are signed or unsigned;
• and
• execution circuitry to perform operations corresponding to the instruction, including to:
• for each row m of the M rows of the first matrix, and for each column n of the N columns of the second matrix:
• for each of K 32-bit elements of the row m of the first matrix:
• multiply eight 4-bit data elements of the 32-bit element of the row m of the first matrix with corresponding ones of eight 4-bit data elements of a corresponding 32-bit element of the column n of the second matrix to generate eight products;
• and
• store a 32-bit result data element, at a row m of the M rows, and a column n of the N columns, of the third matrix, the 32-bit result data element to be based on accumulation of the eight products generated for each of the K 32-bit elements of the row m of the first matrix, with a 32-bit data element corresponding to the row m of the first matrix and the column n of the second matrix.

An apparatus comprising:

• an instruction converter to convert a first instruction into one or more other instructions, the first instruction to indicate a first matrix having M rows by K columns of 32-bit elements each having eight 4-bit data elements, a second matrix having K rows by N columns of 32-bit elements each having eight 4-bit data elements, and a third matrix having M rows by N columns, the instruction having a first indicator to indicate whether the 4-bit data elements of the first matrix are signed or unsigned, and a second indicator to indicate whether the 4-bit data elements of the second matrix are signed or unsigned;
• and
• execution circuitry to perform operations corresponding to the first instruction, including to:
• for each row m of the M rows of the first matrix, and for each column n of the N columns of the second matrix:
• for each of K 32-bit elements of the row m of the first matrix:
• multiply eight 4-bit data elements of the 32-bit element of the row m of the first matrix with corresponding ones of eight 4-bit data elements of a corresponding 32-bit element of the column n of the second matrix to generate eight products;
• and
• store a 32-bit result data element, at a row m of the M rows, and a column n of the N columns, of the third matrix, the 32-bit result data element to be based on accumulation of the eight products generated for each of the K 32-bit elements of the row m of the first matrix, with a 32-bit data element corresponding to the row m of the first matrix and the column n of the second matrix.