Semiconductor device including standard-cell-adapted power grid arrangement

A device comprising:

• a power grid (PG) arrangement including:
• first and second segments in a first conductive layer which are conductive and extend in a first direction;
• the first segments being configured for a first reference voltage and the second segments being configured for a second reference voltage, and
• the first and second segments being interspersed relative to a second direction, the second direction being perpendicular to the first direction;
• and
• third segments in a second conductive layer which are conductive and extend in the second direction,
• the third segments being arranged in sections that extend between intersections with adjacent ones of the first and second segments, and
• as measured in the second direction, a length of each section being sized to keep a resistance of the section below a threshold resistance.

A device comprising:

• a power grid (PG) arrangement including:
• first and second segments in a first conductive layer which are conductive and extend in a first direction,
• the first segments being configured for a first reference voltage and the second segments being configured for a second reference voltage;
• the first and second segments being interspersed relative to a second direction, the second direction being perpendicular to the first direction;
• relative to the second direction,
• the first segments being symmetrically spaced apart relative to each other,
• the second segments being symmetrically spaced apart relative to each other, and
• the second segments being substantially asymmetrically spaced between corresponding adjacent ones of the first segments;
• and
• as measured in the first direction, a length of the first and second segments being sized to substantially avoid electromigration degradation.