Controllable pattern clustering for characterized semiconductor layout designs

A system comprising:

• a memory system configured to store computer-executable instructions;
• and
• a computing system, in response to execution of the computer-executable instructions, is configured to:
• determine principal feature components that describe geometric patterns around points of interest in a semiconductor layout design, wherein the principal feature components include a plurality of topological features for each of the points of interest in the semiconductor layout design, which indicate whether structures are present in different directions around the points of interest, wherein the principal feature components include a plurality of dimensional features for each of the points of interest in the semiconductor layout design, which correspond to measurements associated with the points of interest or the structures present around the points of interest;
• generate a topological signature for each of the points of interest in the semiconductor layout design based on the topological features in the principal feature components;
• select one or more of the dimensional features for each of the points of interest in the semiconductor layout design, wherein the selection corresponds to a level of granularity to cluster the points of interest;
• perform topological clustering for the points of interest, which groups the points of interest into subsets based, at least in part, on the topological signature;
• and
• refine the topological clustering of the points of interest by clustering the points of interest into different subsets based, at least in part, on the selected dimensional features.

An apparatus comprising at least one computer-readable memory device storing instructions configured to cause one or more processing devices to perform operations comprising:

• determining principal feature components that describe geometric patterns around points of interest in a semiconductor layout design, wherein the principal feature components include a plurality of topological features for each of the points of interest in the semiconductor layout design, which indicate whether structures are present in different directions around the points of interest, wherein the principal feature components include a plurality of dimensional features for each of the points of interest in the semiconductor layout design, which correspond to measurements associated with the points of interest or the structures present around the points of interest;
• generating a topological signature for each of the points of interest in the semiconductor layout design based on the topological features in the principal feature components;
• selecting one or more of the dimensional features for each of the points of interest in the semiconductor layout design, wherein the selection corresponds to a level of granularity to cluster the points of interest;
• performing topological clustering for the points of interest, which groups the points of interest into subsets based, at least in part, on the topological signature;
• and
• refining the topological clustering of the points of interest by clustering the points of interest into different subsets based, at least in part, on the selected dimensional features.